4

®

DAC7800, 01, 02

DAC7800

BLOCK DIAGRAM

DAC A

DAC B

DAC A Register

12

12

12

UPD B

I

AGND B

R

V

V

R

I

AGND A

UPD A

OUT B

FB B

REF B

REF A

FB A

OUT A

12

V

DD

9

DGND

10

15

16

14

13

4

3

2

1

6

DAC B Register

Bit 0

Bit 11

Bit 12

Bit 23

7

11

CLR

12

DAC7800

Data

In

5

CLK

8

CS

PIN CONFIGURATION

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

AGND A

CLK

UPD A

Data In

CS

AGND B

I

R

V

V

CLR

UPD B

DGND

OUT A

FB A

REF A

OUT B

DAC7800

Top View

DIP

I

R

V

FB B

REF B

DD

Data In

Bit 0

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18

Bit 17

Bit 16

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

LSB

DAC A

MSB

DAC A

LSB

DAC B

MSB

DAC B

DAC7800 Data Input Sequence

DAC7800 Digital Interface Block Diagram

24-Bit

Shift Register

DAC A Register

UPD A

Data In

CLK

UPD B

LSB

MSB

DAC B Register

LSB

MSB

Bit

23

Bit

12

Bit

11

Bit

0

CLK

DATA INPUT FORMAT

CLK

UPD A

UPD B

CS

CLR

FUNCTION

X

X

X

X

0

All register contents set to 0’s (asynchronous).

X

X

X

1

X

No data transfer.

X

X

0

1

Input data is clocked into input register (location Bit 23) and previous data shifts.

X

0

1

0

1

Input register bits 23 (LSB)—12 (MSB) are loaded into DAC A.

X

1

0

0

1

Input register bits 11 (LSB)—0 (MSB) are loaded into DAC B.

X

0

0

0

1

Input register bits 23 (LSB)—12 (MSB) are loaded into DAC A, and input register bits 11 (LSB)—0 (MSB)

are loaded into DAC B.

X = Don’t care.

means falling edge triggered.

LOGIC TRUTH TABLE