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11

ADS7843

Data Format

The ADS7843 output data is in Straight Binary format as

shown in Figure 9. This figure shows the ideal output code

for the given input voltage and does not include the effects

of offset, gain, or noise.

FIGURE 9. Ideal Input Voltages and Output Codes.

8-Bit Conversion

The ADS7843 provides an 8-bit conversion mode that can

be used when faster throughput is needed and the digital

result is not as critical. By switching to the 8-bit mode, a

conversion is complete four clock cycles earlier. This could

be used in conjunction with serial interfaces that provide 12-

bit transfers or two conversions could be accomplished with

three 8-bit transfers. Not only does this shorten each conver-

sion by four bits (25% faster throughput), but each conver-

sion can actually occur at a faster clock rate. This is because

the internal settling time of the ADS7843 is not as critical—

settling to better than 8 bits is all that is needed. The clock

rate can be as much as 50% faster. The faster clock rate and

fewer clock cycles combine to provide a 2x increase in

conversion rate.

POWER DISSIPATION

There are two major power modes for the ADS7843: full power

When operating at full speed and 16-clocks per conversion (as

shown in Figure 6), the ADS7843 spends most of its time

acquiring or converting. There is little time for auto power-

down, assuming that this mode is active. Therefore, the differ-

ence between full power mode and auto power-down is negli-

gible. If the conversion rate is decreased by simply slowing the

frequency of the DCLK input, the two modes remain approxi-

mately equal. However, if the DCLK frequency is kept at the

maximum rate during a conversion but conversions are simply

done less often, the difference between the two modes is

dramatic.

Figure 10 shows the difference between reducing the DCLK

frequency (“scaling” DCLK to match the conversion rate) or

maintaining DCLK at the highest frequency and reducing

the number of conversions per second. In the later case, the

converter spends an increasing percentage of its time in

power-down mode (assuming the auto power-down mode is

active).

Another important consideration for power dissipation is the

reference mode of the converter. In the single-ended refer-

ence mode, the converter’s internal switches are on only

when the analog input voltage is being acquired (see Figure

5). Thus, the external device, such as a resistive touch

screen, is only powered during the acquisition period. In the

differential reference mode, the external device must be

powered throughout the acquisition and conversion periods

(see Figure 5). If the conversion rate is high, this could

substantially increase power dissipation.

LAYOUT

The following layout suggestions should provide the most

optimum performance from the ADS7843. However, many

portable applications have conflicting requirements con-

cerning power, cost, size, and weight. In general, most

portable devices have fairly “clean” power and grounds

because most of the internal components are very low

power. This situation would mean less bypassing for the

converter’s power and less concern regarding grounding.

Still, each situation is unique and the following suggestions

should be reviewed carefully.

For optimum performance, care should be taken with the

physical layout of the ADS7843 circuitry. The basic SAR

architecture is sensitive to glitches or sudden changes on the

power supply, reference, ground connections, and digital

inputs that occur just prior to latching the output of the

analog comparator. Thus, during any single conversion for

an ‘n-bit’ SAR converter, there are n ‘windows’ in which

0V

FS = Full-Scale Voltage = V

REF

(1)

1 LSB = V

REF

FS – 1 LSB

11...111

11...110

11...101

00...010

00...001

00...000

1 LSB

NOTES: (1) Reference voltage at converter: +REF–(–REF). See Figure 2.

(2) Input voltage at converter, after multiplexer: +IN–(–IN). See Figure 2

FIGURE 10. Supply Current vs Directly Scaling the Fre-

quency of DCLK with Sample Rate or Keeping

DCLK at the Maximum Possible Frequency.

10k

100k

1k

1M

f

100

10

1

1000

f

f

T

+V