®

9

ADS7841

Converter

+IN

CH0

CH1

CH2

CH3

COM

A2-A0

(Shown 001

SGL/DIF

(Shown HIGH)

THEORY OF OPERATION

The ADS7841 is a classic successive approximation register

(SAR) analog-to-digital (A/D) converter. The architecture is

based on capacitive redistribution which inherently includes

a sample/hold function. The converter is fabricated on a

0.6

µs CMOS process.

The basic operation of the ADS7841 is shown in Figure 1.

The device requires an external reference and an external

clock. It operates from a single supply of 2.7V to 5.25V. The

external reference can be any voltage between 100mV and

input range of the converter. The average reference input

current depends on the conversion rate of the ADS7841.

The analog input to the converter is differential and is

provided via a four-channel multiplexer. The input can be

provided in reference to a voltage on the COM pin (which

is generally ground) or differentially by using two of the four

input channels (CH0 - CH3). The particular configuration is

selectable via the digital interface.

ANALOG INPUT

Figure 2 shows a block diagram of the input multiplexer on

the ADS7841. The differential input of the converter is

derived from one of the four inputs in reference to the COM

pin or two of the four inputs. Table I and Table II show the

relationship between the A2, A1, A0, and SGL/DIF control

bits and the configuration of the analog multiplexer. The

control bits are provided serially via the DIN pin, see the

Digital Interface section of this data sheet for more details.

When the converter enters the hold mode, the voltage

difference between the +IN and –IN inputs (see Figure 2) is

captured on the internal capacitor array. The voltage on the

–IN input is limited between –0.2V and 1.25V, allowing the

input to reject small signals which are common to both the

+IN and –IN input. The +IN input has a range of –0.2V to

FIGURE 2. Simplified Diagram of the Analog Input.

A2

A1

A0

CH0

CH1

CH2

CH3

COM

0

0

1

+IN

–IN

1

0

1

–IN

+IN

0

1

0

+IN

–IN

1

1

0

–IN

+IN

TABLE II. Differential Channel Control (SGL/DIF LOW).

A2

A1

A0

CH0

CH1

CH2

CH3

COM

0

0

1

+IN

–IN

1

0

1

+IN

–IN

0

1

0

+IN

–IN

1

1

0

+IN

–IN

TABLE I. Single-Ended Channel Selection (SGL/DIF HIGH).

The input current on the analog inputs depends on the

conversion rate of the device. During the sample period, the

source must charge the internal sampling capacitor (typi-

cally 25pF). After the capacitor has been fully charged, there

is no further input current. The rate of charge transfer from

the analog source to the converter is a function of conver-

sion rate.

FIGURE 1. Basic Operation of the ADS7841.

+V

CC

CH0

CH1

CH2

CH3

COM

SHDN

V

REF

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

DCLK

CS

DIN

BUSY

DOUT

MODE

GND

+V

CC

Serial/Conversion Clock

Chip Select

Serial Data In

Serial Data Out

0.1µF

0.1µF

+2.7V to +5V

ADS7841

Single-ended

or differential

analog inputs

+

1µF

to

10µF