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ADS7832BP Datasheet(PDF) 11 Page - Burr-Brown (TI) |
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ADS7832BP Datasheet(HTML) 11 Page - Burr-Brown (TI) |
11 / 15 page 11 ADS7832 ® and any data written to the SFR has been lost. Thus, the ADS7832 will again be in the Transparent Mode. Writing a LOW to D5 in the SFR resets the Power Fail flag. The Cal Error flag in the SFR is set when an overflow occurs during calibration, which may happen in very noisy systems. It is reset by starting a calibration, and remains low after a calibration without an overflow is completed. Table III shows how instructions can be transferred to the Special Function Register by driving HBE HIGH (with SFR HIGH) and initiating a write cycle (driving WR and CS LOW with RD HIGH.) Note that writing to the SFR also initiates a new conversion. POWER DOWN MODE Writing a HIGH to D3 in the SFR puts the ADS7832 in the Power Down Mode. Power consumption is reduced to 50 µW and D3 remains HIGH. The internal clock and analog circuitry are turned off, although the output registers and SFR can still be accessed normally. To exit Power Down Mode, either write a LOW to D3 in the SFR, or initiate a calibration by sending a LOW to the CAL pin or writing a HIGH to D1. Note that if the power supply falls below 3V and then recovers, a calibration is automatically initiated, and the SFR will be reset. D3 will be HIGH, and the ADS7832 will be in the Power Down Mode. During Power Down Mode, a pulse on CS and WR will initiate a single conversion, then the ADS7832 will revert to power down. Also, writing to D1 and D3 in the SFR will initiate a calibration, do a single conversion and revert to the Power Down Mode, in 4,625 clock cycles. Accurate conver- sion results will be available in the output registers. The activation delay from power down to normal operation is included in the sampling time. No extra time is required, either when coming out of the Power Down Mode or when making a single conversion in the Power Down Mode. SAMPLE/HOLD CONTROL MODE With D2 in the SFR HIGH, a rising edge input on pin 26 will switch the ADS7832 from sample-mode to hold-mode with a 5ns aperture delay. This also initiates a conversion, which will start within 1.5 CLK cycles. This mode allows full control over the sample-to-hold tim- ing, which is especially useful where external events trigger sampling timing. OPERATION CS/WR SFR/HBE D0 D1 D2 D3 D5 D4/D6/D7 Enables Transparent Mode for Data Latches LOW HIGH LOW XXXX LOW Enables Latched Output Mode for Data Latches LOW HIGH HIGH(1) XXXX LOW Initiates Calibration Cycle LOW HIGH X HIGH X X X LOW Activates Sample/Hold Control Mode LOW HIGH X X HIGH(1) X X LOW Activates Power Down Mode(2) LOW HIGH X X X HIGH(1) X LOW Resets Power Fail Flag LOW HIGH X X X X LOW LOW NOTES: (1) Writing a LOW here reactivates the standard mode of operation. (2) In Power Down Mode, a pulse on CS and WR will initiate a single conversion, then the ADS7832 will revert to power down. (3) X means it can be either HIGH or LOW without affecting this action. Writing HIGH to D4 or D6, or writing with SFR HIGH and HBE LOW, may result in unpredictable behavior. These modes are reserved for factory use at this time. TABLE III. Writing to the Special Function Register. FIGURE 5. Writing to the SFR. FIGURE 6. Reading the FSR. In the Sample/Hold Control Mode, pin 26 must be held LOW a minimum of 2.5 µs between conversions to allow accurate acquisition of input signals. Also, offset error will increase in this mode, since auto-zeroing of the comparator is not synchronized to the sampling. Minimum offset is achieved by synchronizing the sampling signal to CLK, whether internal or external. Ideally, the sampling signal rising edge should be delayed 20ns from the falling edge of CLK. This will keep offset error to about 1LSB. In the Sample/Hold Control Mode, a LOW pulse on WR (with CS LOW) will not initiate a conversion, but the rising edge will latch the multiplexer channel according to the inputs on A0 and A1. When changing channels, this must be done at least 2.5 µs before pin 26 goes HIGH (to start a conversion.) D0 - D7 Valid Data SFR HBE WR CS t 5 t 16 t 17 V IL V IH t 2 t 3 t 1 t 6 D0 - D7 SFR Data SFR HBE RD CS t 11 t 14 V IH t 10 t 8 t 11 t 13 t 12 t 12 |
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