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ADS7804 Datasheet(PDF) 4 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation. Click here to check the latest version.
Part No. ADS7804
Description  12-Bit 10ms Sampling CMOS ANALOG-to-DIGITAL CONVERTER
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Maker  BURR-BROWN [Burr-Brown (TI)]
Homepage  http://www.burr-brown.com
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ADS7804 Datasheet(HTML) 4 Page - Burr-Brown (TI)

 
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4
®
ADS7804
1VIN
Analog Input. See Figure 7.
2
AGND1
Analog Ground. Used internally as ground reference point.
3
REF
Reference Input/Output. 2.2
µF tantalum capacitor to ground.
4
CAP
Reference Buffer Capacitor. 2.2
µF tantalum capacitor to ground.
5
AGND2
Analog Ground.
6
D15 (MSB)
O
Data Bit 11. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.
7
D14
O
Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW.
8
D13
O
Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW.
9
D12
O
Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW.
10
D11
O
Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW.
11
D10
O
Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW.
12
D9
O
Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW.
13
D8
O
Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW.
14
DGND
Digital Ground.
15
D7
O
Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW.
16
D6
O
Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW.
17
D5
O
Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW.
18
D4
O
Data Bit 0. Lease Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.
19
D3
O
LOW when CS LOW, R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.
20
D2
O
LOW when CS LOW, R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.
21
D1
O
LOW when CS LOW, R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.
22
D0 (LSB)
O
LOW when CS LOW, R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.
23
BYTE
I
Selects 8 most significant bits (LOW) or 8 least significant bits (HIGH).
24
R/C
I
With CS LOW and BUSY HIGH, a Falling Edge on R/C Initiates a New Conversion. With CS LOW, a rising edge on R/C
enables the parallel output.
25
CS
I
Internally OR’d with R/C. If R/C LOW, a falling edge on CS initiates a new conversion.
26
BUSY
O
At the start of a conversion, BUSY goes LOW and stays LOW until the conversion is completed and the digital outputs
have been updated.
27
VANA
Analog Supply Input. Nominally +5V. Decouple to ground with 0.1
µF ceramic and 10µF tantalum capacitors.
28
VDIG
Digital Supply Input. Nominally +5V. Connect directly to pin 27. Must be
≤ V
ANA.
DIGITAL
PIN #
NAME
I/O
DESCRIPTION
TABLE I. Pin Assignments.
CHARACTERIZATION CURVES
Call factory for updated data sheet which includes character-
ization curves.
PIN CONFIGURATION
V
DIG
V
ANA
BUSY
CS
R/C
BYTE
DZ
DZ
DZ
DZ
D0 (LSB)
D1
D2
D3
V
IN
AGND1
REF
CAP
AGND2
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
DGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS7804


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