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SN54LS109J Datasheet(PDF) 1 Page - Motorola, Inc

Part No. SN54LS109J
Description  DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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SN54LS109J Datasheet(HTML) 1 Page - Motorola, Inc

   
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5-181
FAST AND LS TTL DATA
DUAL JK POSITIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54/ 74LS109A consists of two high speed completely independent
transition clocked JK flip-flops. The clocking operation is independent of rise
and fall times of the clock waveform. The JK design allows operation as a D
flip-flop by simply connecting the J and K pins together.
LOGIC DIAGRAM
SET (SD)
CLEAR (CD)
5(11)
1(15)
CLOCK
4(12)
J
2(14)
K
3(13)
Q
6(10)
Q
7(9)
MODE SELECT — TRUTH TABLE
OPERATING MODE
INPUTS
OUTPUTS
OPERATING MODE
SD
CD
J
K
Q
Q
Set
Reset (Clear)
*Undetermined
Load “1” (Set)
Hold
Toggle
Load “0” (Reset)
L
H
L
H
H
H
H
H
L
L
H
H
H
H
X
X
X
h
l
h
l
X
X
X
h
h
l
l
H
L
H
H
q
q
L
L
H
H
L
q
q
H
* Both outputs will be HIGH while both SD and CD are LOW, but the output states
are unpredictable if SD and CD go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the LOW to HIGH clock transition.
SN54/74LS109A
DUAL JK POSITIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN
Plastic
SN74LSXXXD
SOIC
16
1
D SUFFIX
SOIC
CASE 751B-03
LOGIC SYMBOL
VCC = PIN 16
GND = PIN 8
5
11
2
4
3
6
7
1
14
12
13
10
9
15
J
Q
CP
K
Q
SD
CD
J
Q
CP
K
Q
SD
CD


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