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DP83630SQ Datasheet(PDF) 7 Page - Texas Instruments |
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DP83630SQ Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 135 page  DP83630 www.ti.com SNLS335B – OCTOBER 2010 – REVISED APRIL 2013 2.3.1 IEEE 1588 SYNCHRONIZED CLOCK The DP83630 provides several mechanisms for updating the IEEE 1588 clock based on the synchronization protocol required. These methods are listed below. • Directly Read/Writable • Adjustable by Add/Subtract • Frequency Scalable • Temporary Frequency Control The clock consists of the following fields: Seconds (32–bit field), Nanoseconds (30–bit field), and Fractional Nanoseconds (units of 2-32 ns). A direct set of the time value can be done by setting a new time value. A step adjustment value in nanoseconds may be added to the current value. Note that the adjustment value can be positive or negative. The clock can be programmed to operate at an adjusted frequency value by programming a rate adjustment value. The clock can also be programmed to perform a temporary adjusted frequency value by including a rate adjustment duration. The rate adjustment allows for correction on the order of 2-32 ns per reference clock cycle. The frequency adjustment will allow the clock to correct the offset over time, avoiding any potential side-effects caused by a step adjustment in the time value. The method used to update the clock value may depend on the difference in the values. For example, at the initial synchronization attempt, the clocks may be very far apart, and therefore require a step adjustment or a direct time set. Later, when clocks are very close in value, the temporary rate adjustment method may be the best option. The clock does not support negative time values. If negative time is required in the system, software will have to make conversions from the PHY clock time to actual time. The clock also does not support the upper 16-bits of the seconds field as defined by the specification (Version 2 specifies a 48-bit seconds field). If this value is required to be greater than 0, it will have to be handled by software. Since a rollover of the seconds field only occurs every 136 years, it should not be a significant burden to software. 2.3.1.1 IEEE 1588 Clock Output The DP83630 provides for a synchronized clock signal for use by external devices. The output clock signal can be any frequency generated from 250 MHz divided by n, where n is an integer in the range of 2 to 255. This provides nominal frequencies from 125 MHz down to 980.4 kHz. The clock output signal is controlled by the PTP_COC register. The output clock signal is generated using the rate information in the PTP_RATE registers and is therefore frequency accurate to the 1588 clock time of the device. In addition, if clock time adjustments are made using the Temporary Rate capabilities, then all time adjustments will be tracked by the output clock signal as well. Note that any step adjustment in the 1588 clock time will not be accurately represented on the 1588 clock output signal. 2.3.1.2 IEEE 1588 Clock Input The IEEE 1588 PTP logic operates on a nominal 125 MHz reference clock generated by an internal Phase Generation Module (PGM). However, options are available to use a divided-down version of the PGM clock to reduce power consumption at the expense of precision, or to use an external reference clock of up to 125 MHz in the event the 1588 clock is tracked externally. Copyright © 2010–2013, Texas Instruments Incorporated Device Information 7 Submit Documentation Feedback Product Folder Links: DP83630 |
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