Electronic Components Datasheet Search |
|
CYW181-02SXT Datasheet(PDF) 6 Page - Cypress Semiconductor |
|
CYW181-02SXT Datasheet(HTML) 6 Page - Cypress Semiconductor |
6 / 9 page W181 Document #: 38-07152 Rev. *D Page 6 of 9 Application Information Recommended Circuit Configuration For optimum performance in system applications the power supply decoupling scheme shown in Figure 4 should be used. VDD decoupling is important to both reduce phase jitter and EMI radiation. The 0.1- µF decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the increased trace inductance will negate its decoupling capability. The 10- µF decoupling capacitor shown should be a tantalum type. For further EMI protection, the VDD connection can be made via a ferrite bead, as shown. Recommended Board Layout Figure 5 shows a recommended 2-layer board layout. Notes: 4. The frequency offset (shift) is given with respect to ideal peak value which is the same as input reference frequency in the case of down spread only for W180-01,-02 and -03 products. 5. There is no offset (shift) for center spread for W180-51,-52 and -53 products. AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V ±5% or 5V±10% Parameter Description Test Condition Min. Typ. Max. Unit fIN Input Frequency Input Clock 28 75 MHz fOUT Output Frequency Spread Off 28 75 MHz tR Output Rise Time VDD, 15-pF load 0.8V–2.4V 2 5 ns tF Output Fall Time VDD, 15-pF load 2.4V–0.8V 2 5 ns tOD Output Duty Cycle 15-pF load 40 60 % tID Input Duty Cycle 40 60 % tJCYC Jitter, Cycle-to-Cycle 250 300 ps Harmonic Reduction fout = 40 MHz, third harmonic measured, reference board, 15-pF load 8dB CLKOUT Frequency Offset (Shift)[4,5]: TA =0°C to+70°C,VDD = 3.3V ±5%or 5V±10%(Foronly W181-02, -02and-03products) Parameter Description Frequency Range (MHz) Min. Typ. Max. Unit FOFFSET-1 Frequency Offset (Shift) FS2=0, FS1=0, 28 ≤FIN≤38 –0.8 –1.0 –1.2 % FOFFSET-2 Frequency Offset (Shift) FS2=0, FS1=1, 38 ≤FIN≤48 –1.1 –1.4 –1.7 % FOFFSET-3 Frequency Offset (Shift) FS2=1, FS1=0, 46 ≤FIN≤60 –0.2 –0.5 –0.8 % FOFFSET-4 Frequency Offset (Shift) FS2=1, FS1=1, 58 ≤FIN≤75 –0.8 –1.0 –1.2 % Figure 4. Recommended Circuit Configuration GND 8 7 6 5 1 2 3 4 C1 FB C2 3.3 or 5V System Supply 10-µF Tantalum 0.1 µF Clock Reference Input NC Output R1 |
Similar Part No. - CYW181-02SXT |
|
Similar Description - CYW181-02SXT |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |