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CY62256NLL-70SNXA Datasheet(PDF) 6 Page - Cypress Semiconductor |
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CY62256NLL-70SNXA Datasheet(HTML) 6 Page - Cypress Semiconductor |
6 / 16 page CY62256N Document Number: 001-06511 Rev. *F Page 6 of 16 Switching Characteristics Over the Operating Range Parameter[9] Description CY62256N-55 CY62256N-70 Unit Min Max Min Max Read Cycle tRC Read cycle time 55 – 70 – ns tAA Address to data valid – 55 – 70 ns tOHA Data hold from address change 5 – 5 – ns tACE CE LOW to data valid – 55 – 70 ns tDOE OE LOW to data valid – 25 – 35 ns tLZOE OE LOW to low Z[10] 5– 5– ns tHZOE OE HIGH to high Z[10, 11] –20– 25 ns tLZCE CE LOW to low Z[10] 5– 5– ns tHZCE CE HIGH to high Z[10, 11] –20– 25 ns tPU CE LOW to power-up 0 – 0 – ns tPD CE HIGH to power-down – 55 – 70 ns Write Cycle[12, 13] tWC Write cycle time 55 – 70 – ns tSCE CE LOW to write end 45 – 60 – ns tAW Address setup to write end 45 – 60 – ns tHA Address hold from write end 0 – 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE WE pulse width 40 – 50 – ns tSD Data setup to write end 25 – 30 – ns tHD Data hold from write end 0 – 0 – ns tHZWE WE LOW to high Z[10, 11] –20– 25 ns tLZWE WE HIGH to low Z[10] 5– 5– ns Switching Waveforms Figure 5. Read Cycle No. 1[14, 15] Notes 9. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 100-pF load capacitance. 10. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 11. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 12. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate a Write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the Write. 13. The minimum Write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 14. Device is continuously selected. OE, CE = VIL. 15. WE is HIGH for Read cycle. ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID tRC tAA tOHA |
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