CY62256N

Document Number: 001-06511 Rev. *F

Page 6 of 16

Switching Characteristics

Over the Operating Range

Parameter[9]

Description

CY62256N-55

CY62256N-70

Unit

Min

Max

Min

Max

Read Cycle

Read cycle time

55

–

70

–

ns

Address to data valid

–

55

–

70

ns

Data hold from address change

5

–

5

–

ns

CE LOW to data valid

–

55

–

70

ns

OE LOW to data valid

–

25

–

35

ns

OE LOW to low Z[10]

5–

5–

ns

OE HIGH to high Z[10, 11]

–20–

25

ns

CE LOW to low Z[10]

5–

5–

ns

CE HIGH to high Z[10, 11]

–20–

25

ns

CE LOW to power-up

0

–

0

–

ns

CE HIGH to power-down

–

55

–

70

ns

Write Cycle[12, 13]

Write cycle time

55

–

70

–

ns

CE LOW to write end

45

–

60

–

ns

Address setup to write end

45

–

60

–

ns

Address hold from write end

0

–

0

–

ns

Address setup to write start

0

–

0

–

ns

WE pulse width

40

–

50

–

ns

Data setup to write end

25

–

30

–

ns

Data hold from write end

0

–

0

–

ns

WE LOW to high Z[10, 11]

–20–

25

ns

WE HIGH to low Z[10]

5–

5–

ns

Switching Waveforms

Figure 5. Read Cycle No. 1[14, 15]

Notes

9. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified

12. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can

terminate a Write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the Write.

15. WE is HIGH for Read cycle.

ADDRESS

DATA OUT

PREVIOUS DATA VALID

DATA VALID