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CY14B104NA-BA25IT Datasheet(PDF) 11 Page - Cypress Semiconductor |
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CY14B104NA-BA25IT Datasheet(HTML) 11 Page - Cypress Semiconductor |
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11 / 26 page  CY14B104LA, CY14B104NA Document Number: 001-49918 Rev. *M Page 11 of 26 AC Switching Characteristics Over the Operating Range Parameters [20] Description 20 ns 25 ns 45 ns Unit Cypress Parameter Alt Parameter Min Max Min Max Min Max SRAM Read Cycle tACE tACS Chip enable access time – 20 – 25 – 45 ns tRC[21] tRC Read cycle time 20 – 25 – 45 – ns tAA[22] tAA Address access time – 20 – 25 – 45 ns tDOE tOE Output enable to data valid – 10 – 12 – 20 ns tOHA[22] tOH Output hold after address change 3–3–3 – ns tLZCE[23, 24] tLZ Chip enable to output active 3–3–3 – ns tHZCE[23, 24] tHZ Chip disable to output inactive – 8 – 10 – 15 ns tLZOE[23, 24] tOLZ Output enable to output active 0–0–0 – ns tHZOE[23, 24] tOHZ Output disable to output inactive – 8 – 10 – 15 ns tPU[23] tPA Chip enable to power active 0–0–0 – ns tPD[23] tPS Chip disable to power standby – 20 – 25 – 45 ns tDBE – Byte enable to data valid – 10 – 12 – 20 ns tLZBE[23] – Byte enable to output active 0–0–0 – ns tHZBE[23] – Byte disable to output inactive – 8 – 10 – 15 ns SRAM Write Cycle tWC tWC Write cycle time 20 – 25 – 45 – ns tPWE tWP Write pulse width 15 – 20 – 30 – ns tSCE tCW Chip enable to end of write 15 – 20 – 30 – ns tSD tDW Data setup to end of write 8 – 10 – 15 – ns tHD tDH Data hold after end of write 0–0–0 – ns tAW tAW Address setup to end of write 15 – 20 – 30 – ns tSA tAS Address setup to start of write 0–0–0 – ns tHA tWR Address hold after end of write 0–0–0 – ns tHZWE[23, 24, 25] tWZ Write enable to output disable – 8 – 10 – 15 ns tLZWE[23, 24] tOW Output active after end of write 3–3–3 – ns tBW – Byte enable to end of write 15 – 20 – 30 – ns Switching Waveforms Figure 6. SRAM Read Cycle #1 (Address Controlled) [21, 22, 26] Address Data Output Address Valid Previous Data Valid Output Data Valid t RC t AA t OHA Notes 20. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH and load capacitance shown in Figure 5 on page 10. 21. WE must be HIGH during SRAM read cycles. 22. Device is continuously selected with CE, OE and BHE / BLE LOW. 23. These parameters are guaranteed by design but not tested. 24. Measured ±200 mV from steady state output voltage. 25. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state. 26. HSB must remain HIGH during read and write cycles. |
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