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CY62256NLL-55ZXA Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY62256NLL-55ZXA Datasheet(HTML) 1 Page - Cypress Semiconductor |
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1 / 16 page  CY62256N 256 K (32 K × 8) Static RAM Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-06511 Rev. *F Revised November 9, 2011 256K (32K × 8) Static RAM Features ■ Temperature ranges ❐ Commercial: 0 °C to +70 °C ❐ Industrial: –40 °C to +85 °C ❐ Automotive-A: –40 °C to +85 °C ❐ Automotive-E: –40 °C to +125 °C ■ High speed: 55 ns ■ Voltage range: 4.5 V to 5.5 V operation ■ Low active power ❐ 275 mW (max) ■ Low standby power (LL version) ❐ 82.5 μW (max) ■ Easy memory expansion with CE and OE Features ■ TTL-compatible inputs and outputs ■ Automatic power-down when deselected ■ CMOS for optimum speed and power ■ Available in Pb-free and non Pb-free 28-pin (600-mil) PDIP, 28-pin (300-mil) narrow SOIC, 28-pin TSOP-I, and 28-pin reverse TSOP-I packages Functional Description The CY62256N is a high performance CMOS static RAM organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and tristate drivers. This device has an automatic power-down feature, reducing the power consumption by 99.9 percent when deselected. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH. A9 A8 A7 A6 A5 A4 A3 A2 COLUMN DECODER INPUTBUFFER POWER DOWN WE OE I/O0 CE I/O1 I/O2 I/O3 32K x 8 ARRAY I/O7 I/O6 I/O5 I/O4 A10 Logic Block Diagram |
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