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CY7C1021B-15VE Datasheet(PDF) 4 Page - Cypress Semiconductor |
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CY7C1021B-15VE Datasheet(HTML) 4 Page - Cypress Semiconductor |
4 / 10 page CY7C1021B Document #: 38-05145 Rev. *C Page 4 of 10 AC Test Loads and Waveforms 90% 10% 3.0V GND 90% 10% ALL INPUT PULSES 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE (a) (b) OUTPUT R 481 Ω R 481 Ω R2 255 Ω R2 255 Ω 167 Equivalent to: THÉVENIN EQUIVALENT 1.73V 30 pF Rise Time: 1 V/ns Fall Time: 1 V/ns 90% 10% 3.0V GND 90% 10% ALL INPUT PULSES 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE (a) (b) OUTPUT R 481 Ω R2 255 Ω R2 255 Ω 167 Equivalent to: THÉVENIN EQUIVALENT 1.73V 30 pF Rise Time: 1 V/ns Switching CharacteristicsOver the Operating Range[5] Parameter Description 7C1021B-12 7C1021B-15 Unit Min. Max. Min. Max. Read Cycle tRC Read Cycle Time 12 15 ns tAA Address to Data Valid 12 15 ns tOHA Data Hold from Address Change 3 3 ns tACE CE LOW to Data Valid 12 15 ns tDOE OE LOW to Data Valid 6 7 ns tLZOE OE LOW to Low Z[6] 00 ns tHZOE OE HIGH to High Z[6, 7] 67 ns tLZCE CE LOW to Low Z[6] 33 ns tHZCE CE HIGH to High Z[6, 7] 67 ns tPU CE LOW to Power-Up 0 0 ns tPD CE HIGH to Power-Down 12 15 ns tDBE Byte Enable to Data Valid 6 7 ns tLZBE Byte Enable to Low Z 0 0 ns tHZBE Byte Disable to High Z 6 7 ns Write Cycle[8] tWC Write Cycle Time 12 15 ns tSCE CE LOW to Write End 9 10 ns tAW Address Set-Up to Write End 8 10 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tSD Data Set-Up to Write End 6 8 ns tHD Data Hold from Write End 0 0 ns tLZWE WE HIGH to Low Z[6] 33 ns tHZWE WE LOW to High Z[6, 7] 67 ns tBW Byte Enable to End of Write 8 9 ns Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. [+] Feedback |
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