ATV750/L

2

The ATV750(L) has more flip-flops available than other

PLDs in this density range. Complex state machines are

easily implemented.

Product terms are available providing asynchronous

resets, flip-flop clocks, and output enables. One reset and

one clock term are provided per flip-flop, with one enable

term per output. One product term provides a global syn-

chronous preset. Register preload simplifies testing. The

device has an internal power up clear function.

Logic Options

Output Options

Absolute Maximum Ratings

Temperature Under Bias ............................... -55°C to + 125°C

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Note:

1.

Minimum voltage is -0.6V DC, which may under-

shoot to -2.0V for pulses of less than 20 ns. Max-

imum output pin voltage is Vcc + 0.75V DC,

which may overshoot to 7.0V for pulses of less

than 20 ns.

Storage Temperature .................................... -65°C to + 150°C

Voltage on Any Pin with

Voltage on Input Pins

with Respect to Ground

Programming Voltage with

Combined Terms

Separate Terms

Combined Terms

Separate Terms