ATV750B

9

Preload of Registered Outputs

The ATV750B’s registers are provided with circuitry to

allow loading of each register asynchronously with either a

high or a low. This feature will simplify testing since any

state can be forced into the registers to control test

high; a V

ity. The PRELOAD state is entered by placing a 10.25V to

10.75V signal on pin 8 on DIPs, and lead 10 on SMDs.

When the clock term is pulsed high, the data on the I/O

pins is placed into the register chosen by the Select Pin.

Power Up Reset

The registers in the ATV750Bs are designed to reset during

power up. At a point delayed slightly from V

V

state will depend on the polarity of the output buffer.

This feature is critical for state machine initialization. How-

ever, due to the asynchronous nature of reset and the

uncertainty of how V

lowing conditions are required:

1.

The V

2.

After reset occurs, all input and feedback setup

times must be met before driving the clock terms or

pin high, and

3.

The clock pin, or signals from which clock terms are

derived, must remain stable during t

Level forced on registered

output pin during PRELOAD cycle

Select Pin State

Register #0 State after cycle

Register #1 State after cycle

V

IH

Low

High

X

V

IL

Low

Low

X

V

IH

High

X

High

V

IL

High

X

Low

Parameter

Description

Typ

Max

Units

t

PR

Power-Up Reset Time

600

1000

ns

V

RST

Power-Up Reset Voltage

3.8

4.5

V

Pin Capacitance

f = 1 MHz, T = 25°C

(1)

Typ

Max

Units

Conditions

C

IN

58

pF

V

C

OUT

68

pF

V