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ADP3207D Datasheet(PDF) 31 Page - ON Semiconductor

Part No. ADP3207D
Description  7-Bit Programmable, Multi-Phase Mobile, CPU Synchronous Buck
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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ADP3207D Datasheet(HTML) 31 Page - ON Semiconductor

 
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ADP3207D
http://onsemi.com
31
The best location for the ADP3207D is close to the CPU
corner where all the related signal pins are located: VID0 to
VID6, PSI, VCCSENSE, and VSSSENSE. The components
around the ADP3207D should be located close to the
controller with short traces. The most important traces to
keep short and away from other traces are the FB and
CSSUM pins (refer to Figure 28 for more details on layout
for the CSSUM node.) The MLCC for the VCC decoupling
should be placed as close to the VCC pin as possible. In
addition, the noise filtering capacitor on the TTSENSE pin
should also be as close to that pin as possible.
The output capacitors should be connected as closely as
possible to the load (or connector) that receives the power
(for example, a microprocessor core). If the load is
distributed, then the capacitors should also be distributed,
and generally in proportion to where the load tends to be
more dynamic.
Power Circuitry
Avoid crossing any signal lines over the switching power
path loop. This path should be routed on the PCB to
encompass the shortest possible length to minimize radiated
switching noise energy (that is, EMI) and conduction losses
in the board. Failure to take proper precautions often results
in EMI problems for the entire PC system as well as
noise−related operational problems in the power converter
control circuitry. The switching power path is the loop
formed by the current path through the input capacitors and
the power MOSFETs, including all interconnecting PCB
traces and planes. The use of short and wide interconnection
traces is especially critical in this path for two reasons: it
minimizes the inductance in the switching loop, which can
cause high energy ringing, and it accommodates the high
current demand with minimal voltage loss.
Whenever a power−dissipating component (for example,
a power MOSFET) is soldered to a PCB, the liberal use of
vias, both directly on the mounting pad and immediately
surrounding it, is recommended. Two important reasons for
this are: improved current rating through the vias, and
improved thermal performance from vias extended to the
opposite side of the PCB where a plane can more readily
transfer the heat to the air. Make a mirror image of any pad
being used to heat sink the MOSFETs on the opposite side
of the PCB to achieve the best thermal dissipation to the air
around the board. To further improve thermal performance,
the largest possible pad area should be used.
The output power path should also be routed to encompass
a short distance. The output power path is formed by the
current path through the inductor, the output capacitors, and
the load.
For best EMI containment, use a solid power ground plane
as one of the inner layers extending fully under all the power
components.
It is important for conversion efficiency that MOSFET
drivers, such as ADP3611, are placed as close to the
MOSFETs as possible. Thick and short traces are required
between the driver and MOSFET gate, especially for the SR
MOSFETs. Ground the MOSFET driver’s GND pin through
the closest vias.
Signal Circuitry
The output voltage is sensed and regulated between the FB
pin and the FBRTN pin, which connects to the signal ground
at the load. To avoid differential mode noise pickup in the
sensed signal, the loop area should be small. Therefore, route
the FB and FBRTN traces adjacent to each other atop the
power ground plane back to the controller. To filter any noise
from the FBRTN trace, using a 1000 pF MLCC is suggested.
It should be placed between the FBRTN pin and local ground
and as close to the FBRTN pin as possible.
Connect the feedback traces from the switch nodes as
close as possible to the inductor. The CSREF signal should
be Kelvin connected to the center point of the copper bar,
which is the VCore common node for the inductors of all
phases.
On the back side of the ADP3207D package, a metal pad
can be used as the device heat sink. In addition, running vias
under the ADP3207D is not recommended because the
metal pad can cause shorting between vias.
ORDERING INFORMATION
Device
Temperature Range
Package
Shipping
ADP3207DJCPZ−RL
0°C to 100°C
LFCSP40
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*The “Z” suffix indicates Pb−Free part.


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