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ADP3207D Datasheet(PDF) 30 Page - ON Semiconductor
ONSEMI [ON Semiconductor]
ADP3207D Datasheet(HTML) 30 Page - ON Semiconductor
/ 32 page
15. Users should see a waveform that is similar to the
one in Figure 33. Use the horizontal cursors to
as shown. Do not
measure the undershoot or overshoot that occurs
immediately after the step.
16. If the V
are different by more
than a couple of mV, use the following to adjust C
(Note that users may need to parallel different values
to get the right one due to the limited standard
capacitor values available. It is also wise to have
locations for two capacitors in the layout for this.)
17. Repeat Step 15 and Step 16. Repeat adjustments if
necessary. Once completed, do not change C
the rest of the procedure.
18. Set dynamic load step to maximum step size. Do not
use a step size larger than needed. Verify that the
output waveform is square, which means V
are equal. Note: Make sure that the
load step slew rate and turn−on are set for a slew
rate of ~150 A/
ms to 250 A/ms (for example, a load
step of 50 A should take 200 ns to 300 ns) with no
overshoot. Some dynamic loads have an excessive
turn−on overshoot if a minimum current is not set
properly (this is an issue if using a V
Initial Transient Setting
19. With dynamic load still set at the maximum step
size, expand the scope time scale to see 2
ms/div. A waveform that has two overshoots and
one minor undershoot can result (see Figure 33).
is the final desired value.
Figure 33. Transient Setting Waveform, Load Step
20. If both overshoots are larger than desired, make
the following adjustments in the order they appear.
Note that if these adjustments do not change the
response, users are limited by the output
decoupling. In addition, check the output response
each time a change is made, as well as the
switching nodes to make sure they are still stable.
a. Make ramp resistor larger by 25% (R
b. For V
, increase C
or increase switching
c. For V
, increase R
and decrease C
both by 25%.
21. For load release (see Figure 34), if V
larger than the IMVP−6 specification, there is not
enough output capacitance. Either more
capacitance is needed or the inductor values need
to be smaller. If the inductors are changed, then
start the design over using Equations 1 to 38 and
this tuning guide.
Figure 34. Transient Setting Waveform, Load Release
Layout and Component Placement
The following guidelines are recommended for optimal
performance of a switching regulator in a PC system.
For effective results, at least a 4−layer PCB is
recommended. This allows the needed versatility for control
circuitry interconnections with optimal placement, power
planes for ground, input and output power, and wide
interconnection traces in the rest of the power delivery current
paths. Note that each square unit of 1 ounce copper trace has
a resistance of ~0.53 m
W at room temperature.
When high currents need to be routed between PCB layers,
vias should be used liberally to create several parallel current
paths so that the resistance and inductance introduced by
these current paths are minimized, and the via current rating
is not exceeded.
If critical signal lines (including the output voltage sense
lines of the ADP3207D) must cross through power circuitry,
a signal ground plane should be interposed between those
signal lines and the traces of the power circuitry. This serves
as a shield to minimize noise injection into the signals at the
expense of making signal ground a bit noisier.
An analog ground plane should be used around and under
the ADP3207D for referencing the components associated
with the controller. Tie this plane to the nearest output
decoupling capacitor ground. It should not be tied to any other
power circuitry to prevent power currents from flowing in it.
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