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ADP3207D Datasheet(PDF) 29 Page - ON Semiconductor

Part No. ADP3207D
Description  7-Bit Programmable, Multi-Phase Mobile, CPU Synchronous Buck
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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ADP3207D Datasheet(HTML) 29 Page - ON Semiconductor

 
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ADP3207D
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29
Selecting Thermal Monitor Components
For single−point hot spot thermal monitoring, simply set
RTTSET1 equal to the NTC thermistor’s resistance at the
alarm temperature (see Figure 30). For example, if the
VRTT alarm temperature is 100
°C using a Vishey thermistor
(NTHS−0603N011003J) with a resistance of 100 k
W at
25
°C, and 6.8 kW at 100°C, simply set RTTSET1 = RTH1
(100
°C) to 6.8 kW.
Figure 30. Single−Point Thermal Monitoring
+
R
R
VCC
TTSN
VRTT
ADP3207D
5.0 V
RTTSET1
RTH
CTT
31
30
Multiple−point hot spot thermal monitoring can be
implemented as shown in Figure 31. If any of the monitored
hot spots reach alarm temperature, the VRTT signal is asserted.
The following calculation sets the alarm temperature:
RTTSET1 +
1
2 )
VFD
VREF
1
2 *
VFD
VREF
RTH1ALARMTEMPERATURE
(eq. 41)
Where VFD is the forward drop voltage of the parallel diode.
Because the forward current is very small, the forward drop
voltage is very low (100 mV). Assuming the same 100
°C
alarm temperature used in the single−spot thermal monitoring
example, and the same Vishay thermistor, then Equation 41
leads to RTTSET = 7.37 kW, whose closest standard resistor is
7.32 k
W (1%).
Figure 31. Multiple−Point Thermal Monitoring
+
R
R
31
30
VCC
TTSN
5 V
RTTSET1
RTH1
RTTSET2
RTTSET3
RTH2
RTH3
The number of hot spots monitored is not limited. The
alarm temperature of each hot spot can be set differently by
playing different RTTSET1, RTTSET2, and RTTSETn.
Tuning Procedure for ADP3207D
1. Build the circuit based on compensation values
computed from Equations 1 to 41.
2. Hook−up the dc load to the circuit. Turn the circuit
on and verify operation. Check for jitter at no load
and full load.
DC Loadline Setting
3. Measure the output voltage at no load (VNL). Verify
that it is within tolerance.
4. Measure the output voltage at full load and at cold
(VFLCOLD). Let the board set for ~10 minutes at
full load and measure the output (VFLHOT). If there
is a change of more than a few mV, then adjust
RCS1 and RCS2 using Equations 42 and 43.
RCS2(NEW) + RCS2(OLD)
VNL * VFLCOLD
VNL * VFLHOT
(eq. 42)
5. Repeat Step 4 until cold and hot voltage
measurements remain the same.
6. Measure output voltage from no load to full load
using 5 A steps. Compute the load line slope for
each change and then average it to get the overall
load line slope (ROMEAS).
7. If ROMEAS is off from RO by more than 0.05 mW,
use the following to adjust the RPH values:
RPH(NEW) + RPH(OLD)
ROMEAS
RO
(eq. 43)
8. Repeat Steps 6 and 7 to check load line and repeat
adjustments if necessary.
9. Once completed with dc load line adjustment, do not
change RPH, RCS1, RCS2, or RTH for the rest of
procedure.
10. Measure output ripple at no load and full load with a
scope to make sure it is within specification.
Figure 32. AC Loadline Waveform
VDCDRP
VACDRP
AC Loadline Setting
11. Remove the dc load from the circuit and hook up
the dynamic load.
12. Hook up the scope to the output voltage and set it
to dc coupling with the time scale at 100
ms/div.
13. Set the dynamic load for a transient step of about
40 A at 1 kHz with a 50% duty cycle.
14. Measure the output waveform (using the dc offset
on scope to see the waveform, if necessary). Try to
use the vertical scale of 100 mV/div or finer.


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