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ADP3207D Datasheet(PDF) 27 Page  ON Semiconductor 

ADP3207D Datasheet(HTML) 27 Page  ON Semiconductor 
27 / 32 page ADP3207D http://onsemi.com 27 ramp size that gives an optimal balance for good stability, transient response, and thermal balance. COMP Pin Ramp There is a ramp signal on the COMP pin due to the droop voltage and output voltage ramps. This ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the PWM input: VRT + VR 1 * 2 (1*n D) n fSW CX RO (eq. 21) For this example, the overall ramp signal is found to be 2.2 V. Setting the Switching Frequency for RPM Mode Operation of Phase. During the RPM mode operation of Phase 1, the ADP3207D runs in pseudo constant frequency, given that the load current is high enough for continuous current mode. While in discontinuous current mode, the switching frequency is reduced with the load current in a linear manner. When considering power conversion efficiency in light load, lower switching frequency is usually preferred for RPM mode. However, the VCore ripple specification in the IMVP−6 sets the limitation for lowest switching frequency. Therefore, depending on the inductor and output capacitors, the switching frequency in RPM mode can be equal, larger, or smaller than its counterpart in PWM mode. A resistor from RPM to GND sets the pseudo constant frequency as following: RRPM + 2 RT VVID ) 1.0 V AR (1 * D) VVID RR CR fSW (eq. 22) * 0.5 kW Where: AR is the internal ramp amplifier gain. CR is the internal ramp capacitor value. RR is an external resistor on the RAMPADJ pin to set the internal ramp magnitude. Because RR = 280 kW, the following resistance sets up 300 kHz switching frequency in RPM operation: RRPM + 2 280 kW 1.150 V ) 1.0 V 0.5 (1 * 0.061) 1.150 462 kW 5pF 300 kHz * 5 W + 202 kW (eq. 23) Output Current Monitor The ADP3207D has output current monitor. The IMON pin sources a current proportional to the total inductor current. A resistor, RMON, from IMON to FBRTN sets the gain of the output current monitor. A 0.1 mF is placed in parallel with RMON to filter the inductor current ripple and high frequency load transients. Since the IMON pin is connected directly to the CPU, it is clamped to prevent it from going above 1.15 V. The IMON pin current is equal to the RLIM times a fixed gain of 10. RMON can be found using the following equation: RMON + 1.15 V RLIM 10 RO IFS (eq. 24) Where: RMON is the current monitor resistor. RMON is connected from IMON pin to FBRTN. RLIM is the current limit resistor. RO is the output load line resistance. IFS is the output current when the voltage on IMON is at full scale. Current Limit Setpoint To select the current limit setpoint, we need to find the resistor value for RLIM. The current limit threshold for the ADP3207D is set when the current in RLIM is equal to the internal reference current of 20 mA. The current in RLIM is equal to the inductor current times RO. RLIM can be found using the following equation: RLIM + ILIM RO 20 mA (eq. 25) Where: RLIM is the current limit resistor. RLIM is connected from the ILIM pin to ground. RO is the output load line resistance. ILIM is the current limit set point. This is the peak inductor current that will trip current limit. In this example, if choosing 55 A for ILIM, RLIM is 5.775 k W, which is close to a standard 1% resistance of 5.76 k W. The per phase current limit described earlier has its limit determined by the following: IPHLIM ^ VCOMP(MAX) * VR * VBIAS AD RDS(MAX) ) IR 2 (eq. 26) For the ADP3207D, the maximum COMP voltage (VCOMP(MAX)) is 3.3 V, the COMP pin bias voltage (VBIAS) is 1.0 V, and the current balancing amplifier gain (AD) is 5. Using a VR of 0.55 V, and a RDS(MAX) of 3.8 mW (low−side on−resistance at 150 °C) results in a per phase limit of 85 A. Although this number seems high, this current level can only be reached with a absolute short at the output and the current limit latchoff function shutting down the regulator before overheating occurs. This limit can be adjusted by changing the ramp voltage VR. However, users should not set the per phase limit lower than the average per phase current (ILIM/n). There is also a per phase initial duty−cycle limit at maximum input voltage: DLIM + DMIN VCOMP(MAX) * VBIAS VR (eq. 27) For this example, the duty−cycle limit at maximum input voltage is found to be 0.25 when D is 0.061. Feedback Loop Compensation Design Optimized compensation of the ADP3207D allows the best possible response of the regulator’s output to a load change. The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output 
