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ADP3207D Datasheet(PDF) 25 Page  ON Semiconductor 

ADP3207D Datasheet(HTML) 25 Page  ON Semiconductor 
25 / 32 page ADP3207D http://onsemi.com 25 COUT Selection The required output decoupling for processors and platforms is typically recommended by Intel. The following guidelines can also be used if both bulk and ceramic capacitors are in the system: • Select the total amount of ceramic capacitance. This is based on the number and type of capacitors to be used. The best location for ceramics is inside the socket; 20 pieces of Size 0805 being the physical limit. Additional capacitors can be placed along the outer edge of the socket. • Select the number of ceramics and find the total ceramic capacitance (CZ). Combined ceramic values of 200 mF to 300 mF are recommended and are usually made up of multiple 10 mF or 22 mF capacitors. • Note that there is an upper limit imposed on the total amount of bulk capacitance (CX) when considering the VID OTF output voltage stepping (voltage step VV in time tV with error of VERR), and also a lower limit based on meeting the critical capacitance for load release at a given maximum load step DIO. For a step−off load current, the current version of the IMVP−6 specification allows a maximum VCore overshoot (VOSMAX) of 10 mV, plus 1.5% of the VID voltage. For example, if the VID is 1.150 V, then the largest overshoot allowed is 50 mV. Cx(MIN) w L DIO n RO ) VOSMAX DIO VVVID * Cz (eq. 11) CX(MAX) v L nK2RO 2 Vv VVID (eq. 12) 1 ) tv VVID Vv nKRO L 2 * 1 * Cz where: K + −1n VERR VV (eq. 13) To meet the conditions of these equations and transient response, the ESR of the bulk capacitor bank (RX) should be less than two times the droop resistance, RO. If the CX(MIN) is larger than the CX(MAX), the system does not meet the VID OTF and/or deeper sleep exit specification and can require a smaller inductor or more phases (the switching frequency can also have to be increased to keep the output ripple the same). For example, if using 32 pieces of 10 mF 0805 MLC capacitors (CZ = 320 mF), the fastest VID voltage change is the exit of deeper sleep, and the VCore change is 220 mV in 22 ms with a setting error of 10 mV. Where K = 3.1, solving for the bulk capacitance yields. CX(MIN) w 360 nH @ 34.5 A 2 @ 2.1 mW ) 50 mV 34.5 A @ 1.150 V * 320 mF + 0.8 mF CX(MAX) v 360 nH 220 mV 2 3.12 (2.1 mW)2 1.150 V 1 ) 22 ms 1.150 V 2 3.1 2.1 mW 220 mV 360 nH 2 * 1 * 320 mF + 2.3 mF Using three 330 mF Panasonic SP capacitors with a typical ESR of 6 m W each, yields CX = 0.99 mF with an RX = 2.0 mW. One last check should be made to ensure that the ESL of the bulk capacitors (LX) is low enough to limit the high frequency ringing during a load change. This is tested using: LX v C320 mF (2.1 mW)2 2 + 2nH (eq. 14) LX v C2 RO 2 Q2 Where: Q is limited to the √2 to ensure a critically damped system. In this example, LX is about 330 pH for the three SP capacitors, which satisfies this limitation. If the LX of the chosen bulk capacitor bank is too large, the number of ceramic capacitors may need to be increased if there is excessive ringing. Note that for this multi−mode control technique, an all−ceramic capacitor design can be used as long as the conditions of Equations 11, 12, and 13 are satisfied. Power MOSFETs For normal 20 A per phase application, the N−channel power MOSFETs are selected for two high−side switches and two low−side switches per phase. The main selection parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). Because the gate drive voltage (the supply voltage to the ADP3611) is 5.0 V, logic−level threshold MOSFETs must be used. The maximum output current IO determines the RDS(on) requirement for the low−side (synchronous) MOSFETs. In the ADP3207D, currents are balanced between phases; the current in each low−side MOSFET is the output current divided by the total number of MOSFETs (nSF). With conduction losses being dominant, Equation 15 shows the total power dissipated in each synchronous MOSFET in terms of the ripple current per phase (IR) and average total output current (IO): PSF + (1 * D) IO nSF ) 1 12 n IR nSF 2 RDS(SF) (eq. 15) 
