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ADP3207D Datasheet(PDF) 16 Page - ON Semiconductor
ONSEMI [ON Semiconductor]
ADP3207D Datasheet(HTML) 16 Page - ON Semiconductor
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then given as the voltage difference of CSREF − LLSET. The
configuration in the previous paragraph makes it possible for
the load line slope to be set independent of the current limit
threshold. In the event that the current limit threshold and load
line do not have to be independent, the resistor divider
between CSREF and CSCOMP can be omitted and the
CSCOMP pin can be connected directly to LLSET. To disable
voltage positioning entirely (that is, to set no load line), tie
LLSET to CSREF.
To provide the best accuracy for current sensing, the CSA
is designed to have a low offset input voltage. In addition, the
sensing gain is set by an external resistor ratio.
Active Impedance Control Mode
To control the dynamic output voltage droop as a function
of the output current, the signal proportional to the total
output current is converted to a voltage that appears between
CSREF and LLINE. This voltage can be scaled to equal the
droop voltage, which is calculated by multiplying the droop
impedance of the regulator with the output current. The droop
voltage is then used as the control voltage of the PWM
regulator. The droop voltage is subtracted from the DAC
reference output voltage and determines the voltage
positioning setpoint. The setup results in an enhanced feed
Current Control Mode and Thermal Balance
The ADP3207D has individual inputs for monitoring the
current in each phase. The phase current information is
combined with an internal ramp to create a current balancing
feedback system that is optimized for initial current accuracy
and dynamic thermal balance. The current balance
information is independent of the total inductor current
information used for voltage positioning described in the
Active Impedance Control Mode section.
The magnitude of the internal ramp can be set so the
transient response of the system becomes optimal. The
ADP3207D also monitors the supply voltage to achieve
feed−forward control whenever the supply voltage changes.
A resistor connected from the power input voltage rail to the
RAMP pin determines the slope of the internal PWM ramp.
Detailed information about programming the ramp is given
in the Ramp Resistor Selection section.
External resistors are in series with the SW1 pin, SW2 pin,
and the SW3 pin to create an intentional current imbalance.
Such a condition can exist when one phase has better cooling
and supports higher currents than the other phase. Resistor
RSW2 and Resistor RSW3 (see the Typical Application
Circuit in Figure 28) can be used to adjust thermal balance.
It is recommended to add these resistors during the initial
design to make sure placeholders are provided in the layout.
To increase the current in any given phase, users should
make RSW for that phase larger (that is, make RSW = 1.5 k
for the hottest phase and do not change it during balance
optimization). Increasing RSW to 1.5 k
W makes a substantial
increase in phase current. Increase each RSW value by small
amounts to achieve thermal balance starting with the coolest
If adjusting current balance between phases is not needed,
RSW should be 1 k
W for all phases.
Voltage Control Mode
A high gain bandwidth error amplifier is used for the
voltage−mode control loop. The non−inverting input voltage
is set via the 7−bit VID DAC. The VID codes are listed in
Table 3. The non−inverting input voltage is offset by the
droop voltage as a function of current, commonly known as
active voltage positioning. The output of the error amplifier
is the COMP pin, which sets the termination voltage for the
internal PWM ramps.
The negative input, FB, is tied to the output sense location
through a resistor, RB, for sensing and controlling the output
voltage at the remote sense point. The main loop
compensation is incorporated in the feedback network
connected between FB and COMP.
Enhanced PWM Mode
Enhanced PWM mode is intended to improve the transient
response to a load step up. In traditional PWM controllers,
when a load step up occurred, the controller had to wait until
the next turn on of the PWM signal to respond to the load
change. Enhanced PWM mode allows the controller to
respond immediately when a load step up occurs. This allows
the phases to respond when the load increase transition takes
place. EWPM is disabled in RPM operation.
The power−good comparator monitors the output voltage
via the CSREF pin. The PWRGD pin is an open drain output
that can be pulled up through an external resistor to a voltage
rail that is not necessarily the same V
voltage rail of the
controller. Logic high level indicates that the output voltage
is within the voltage limits defined by a window around the
VID voltage setting. PWRGD goes low when the output
voltage is outside of that window.
Following the IMVP−6 specification, the PWRGD window
is defined as −300 mV below and +200 mV above the actual
VID DAC output voltage. For any DAC voltage below
300 mV, only the upper limit of the PWRGD window is
monitored. To prevent false alarm, the power−good circuit is
masked during various system transitions, including any VID
change and entrance/exit out of deeper sleep. The duration of
the PWRGD mask is set by an internal timer to be about
ms. In conditions where a larger than 200 mV voltage drop
occurs during deeper sleep entry or slow deeper sleep exit, the
duration of PWRGD masking is extended by an internal logic
Powerup Sequence and Soft−Start
The power−on, ramp−up time of the output voltage is set
internally. The reference voltage of the voltage error amplifier
is connected to an internal DAC. This DAC converts the VID
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