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ADP3207D Datasheet(PDF) 15 Page - ON Semiconductor

Part No. ADP3207D
Description  7-Bit Programmable, Multi-Phase Mobile, CPU Synchronous Buck
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Maker  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
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ADP3207D Datasheet(HTML) 15 Page - ON Semiconductor

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ADP3207D
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Table 1. Phase Number and Operation Modes
PSI
DPRSLP
VID Transient
Period (Note 1)
Hit Current
Limit
No. of Phases
Selected by User
No. of Phases
in Operation
Operation Mode
DNC
DNC
Yes
DNC
N 3, 2, or 1
N
PWM, CCM Only
1
0
No
DNC
N 3, 2, or 1
N
PWM, CCM Only
0
0
No
No
DNC
Phase 1 only
RPM, CCM Only
0
0
No
Yes
DNC
N
PWM, CCM Only
DNC
1
No
No
DNC
Phase 1 only
RPM, Automatic
CCM / DCM
DNC
1
No
Yes
DNC
N
PWM, CCM Only
1. VID transient period is the time following any VID change, including entrance and exit of deeper sleep mode. The duration of VID transient
period is the same as that of PWRGD masking time.
2. DNC = Do Not Care.
3. CCM = Continuous Conduction Mode.
4. DCM = Discontinuous Conduction Mode.
Switch Frequency Setting
Master Clock Frequency for PWM Mode
The clock frequency of the ADP3207D is set by an
external resistor connected from the RT pin to ground. The
frequency varies with the VID voltage; the lower the VID
voltage, the lower the clock frequency. The variation of
clock frequency with VID voltage makes VCore ripple
remain constant and improves power conversion efficiency
at a lower VID voltage.
To determine the switching frequency per phase, the clock
is divided by the number of phases in use. If PWM3 is pulled
up to VCC, then the master clock is divided by 2 for the
frequency of the remaining phases. If PWM2 and PWM3 are
pulled up to VCC, then the switching frequency of a Phase 1
equals the master clock frequency. If all phases are in use,
divide by 3.
Switching Frequency for RPM Mode−Phase 1
When ADP3207D operates in single−phase RPM mode, its
switching frequency is not controlled by the master clock, but
by the ripple voltage on the COMP pin. The PWM1 pin is set
high each time the COMP pin voltage rises to a voltage limit
determined by the VID voltage and the external resistance
connected between Pin RPM and ground. Whenever PWM1
pin is high, an internal ramp signal rises at a slew rate
programmed by the current flowing into the RAMP pin. Once
this internal ramp signal hits the COMP pin voltage, the
PWM1 pin is reset to low.
In continuous current mode, the switching frequency of
RPM operation is maintained almost constantly. While in
discontinuous current mode, the switching frequency reduces
with the load current.
Output Voltage Differential Sensing
The ADP3207D combines differential sensing with a high
accuracy, VID DAC, precision REF output and a low offset
error amplifier to meet the rigorous accuracy requirement of
the Intel IMVP−6 specification. In steady−state, the VID
DAC and error amplifier meet the worst−case error
specification of
$10 mV over the full operating output
voltage and temperature range.
The CPU core output voltage is sensed between the FB pin
and the FBRTN pin. Connect FB through a resistor to the
positive regulation point, usually the VCC remote sense pin of
the microprocessor. Connect FBRTN directly to the negative
remote sense point, the VSS sense point of the CPU. The
internal VID DAC and precision voltage reference are
referenced to FBRTN and have a maximum current of 200
mA
to guarantee accurate remote sensing.
Output Current Sensing
The ADP3207D provides a dedicated current sense
amplifier (CSA) to monitor the total output current of the
converter for proper voltage positioning vs. load current and
for current limit detection. Sensing the load current being
delivered to the load is inherently more accurate than
detecting peak current or sampling the current across a sense
element, such as the low−side MOSFET. The current sense
amplifier can be configured several ways depending on
system requirements, including:
Output inductor ESR sensing without use of a
thermistor for lowest cost
Output inductor ESR sensing with use of a thermistor
that tracks inductor temperature to improve accuracy
Discrete resistor sensing for highest accuracy
The positive input of the CSA is connected to the CSREF
pin, which is connected to the output voltage. At the negative
input CSSUM pin of the CSA, signals from the sensing
element (that is, in case of inductor RDC sensing, signals
from the switch node side of the output inductors) are
summed together by using series summing resistors. The
feedback resistor between CSCOMP and CSSUM sets the
gain of the current sense amplifier, and a filter capacitor is
placed in parallel with this resistor. The current information
is then given as the voltage difference between CSREF and
CSCOMP. This signal is used internally as a differential input
for the current limit comparator.
An additional resistor divider connected between CSREF
and CSCOMP with the midpoint connected to LLSET can be
used to set the load line required by the microprocessor
specification. The current information for load line setting is


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