Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

ATMEGA603 Datasheet(PDF) 5 Page - ATMEL Corporation

Part No. ATMEGA603
Description  8-Bit Microcontroller with 64K/128K Bytes In-System Programmable Flash
Download  10 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATMEGA603 Datasheet(HTML) 5 Page - ATMEL Corporation

  ATMEGA603 Datasheet HTML 1Page - ATMEL Corporation ATMEGA603 Datasheet HTML 2Page - ATMEL Corporation ATMEGA603 Datasheet HTML 3Page - ATMEL Corporation ATMEGA603 Datasheet HTML 4Page - ATMEL Corporation ATMEGA603 Datasheet HTML 5Page - ATMEL Corporation ATMEGA603 Datasheet HTML 6Page - ATMEL Corporation ATMEGA603 Datasheet HTML 7Page - ATMEL Corporation ATMEGA603 Datasheet HTML 8Page - ATMEL Corporation ATMEGA603 Datasheet HTML 9Page - ATMEL Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 10 page
background image
ATmega603(L) and ATmega103(L)
5
Figure 4. The ATmega603/103 AVR Enhanced RISC Architecture
The AVR uses a Harvard architecture concept - with sepa-
rate memories and buses for program and data. The pro-
gram memory is executed with a single level pipelining.
While one instruction is being executed, the next instruction
is pre-fetched from the program memory. This concept
enables instructions to be executed in every clock cycle.
The program memory is in-system programmable Flash
memory. With a few exceptions, AVR instructions have a
single 16-bit word format, meaning that every program
memory address contains a single 16-bit instruction.
During interrupts and subroutine calls, the return address
program counter (PC) is stored on the stack. The stack is
effectively allocated in the general data SRAM, and conse-
quently the stack size is only limited by the total SRAM size
and the usage of the SRAM. All user programs must initial-
ize the SP in the reset routine (before subroutines or inter-
rupts are executed). The 16-bit stack pointer SP is
read/write accessible in the I/O space.
The 4000 bytes data SRAM can be easily accessed
through the five different addressing modes supported in
the AVR architecture.
A flexible interrupt module has its control registers in the
I/O space with an additional global interrupt enable bit in
the status register. All the different interrupts have a sepa-
rate interrupt vector in the interrupt vector table at the
beginning of the program memory. The different interrupts
have priority in accordance with their interrupt vector posi-
tion. The lower the interrupt vector address, the higher the
priority.
The memory spaces in the AVR architecture are all linear
and regular memory maps.
The General Purpose Register File
Figure 5 shows the structure of the 32 general purpose
working registers in the CPU.
32K/64K x 16
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registers
ALU
Status
and Test
2K/4K x 8
EEPROM
Peripherals
Data Bus 8-bit
AVR ATmega603/103 Architecture
4K x 8
Data
SRAM


Html Pages

1  2  3  4  5  6  7  8  9  10 


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn