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ATMEGA163 Datasheet(PDF) 74 Page - ATMEL Corporation |
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ATMEGA163 Datasheet(HTML) 74 Page - ATMEL Corporation |
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74 / 187 page  74 ATmega163(L) 1142E–AVR–02/03 set), the 9th bit is one for an address byte and zero for a data byte, whereas the stop bit is always high. The following procedure should be used to exchange data in Multi-Processor Communi- cation mode: 1. All Slave MCUs are in Multi-Processor Communication mode (MPCM in UCSRA is set). 2. The Master MCU sends an address byte, and all slaves receive and read this byte. In the Slave MCUs, the RXC Flag in UCSRA will be set as normal. 3. Each Slave MCU reads the UDR Register and determines if it has been selected. If so, it clears the MPCM bit in UCSRA, otherwise it waits for the next address byte. 4. For each received data byte, the receiving MCU will set the Receive Complete Flag (RXC in UCSRA). In 8-bit mode, the receiving MCU will also generate a Framing Error (FE in UCSRA set), since the stop bit is zero. The other slave MCUs, which still have the MPCM bit set, will ignore the data byte. In this case, the UDR Register and the RXC or FE Flags will not be affected. 5. After the last byte has been transferred, the process repeats from step 2. UART Control UART I/O Data Register – UDR The UDR Register is actually two physically separate registers sharing the same I/O address. When writing to the register, the UART Transmit Data Register is written. When reading from UDR, the UART Receive Data Register is read. UART Control and Status Register A – UCSRA • Bit 7 – RXC: UART Receive Complete This bit is set (one) when a received character is transferred from the Receiver Shift Register to UDR. The bit is set regardless of any detected framing errors. When the RXCIE bit in UCR is set, the UART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR. When interrupt-driven data reception is used, the UART Receive Complete Interrupt routine must read UDR in order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates. • Bit 6 – TXC: UART Transmit Complete This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift Register has been shifted out and no new data has been written to UDR. This Flag is especially useful in half-duplex communications interfaces, where a transmitting appli- cation must enter receive mode and free the communications bus immediately after completing the transmission. Bit 7654 3210 $0C ($2C) MSB LSB UDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0000 0000 Bit 7654 3210 $0B ($2B) RXC TXC UDRE FE OR – U2X MPCM UCSRA Read/Write r R/W RRRR R/W R/W Initial Value 0000 0000 |
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