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AD1845JSTZ Datasheet(PDF) 7 Page - Analog Devices |
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AD1845JSTZ Datasheet(HTML) 7 Page - Analog Devices |
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7 / 40 page  AD1845 –7– REV. C PIN FUNCTION DESCRIPTIONS Parallel Interface Pin Name PLCC TQFP I/O Description CDRQ 12 7 O Capture Data Request. The assertion of this signal HI indicates that the codec has a cap- tured audio sample from the ADC ready for transfer. This signal will remain asserted until the internal capture FIFO is empty. CDAK 11 6 I Capture Data Acknowledge. The assertion of this active LO signal indicates that the RD cycle occurring is a DMA read from the capture buffer. PDRQ 14 9 O Playback Data Request. The assertion of this signal HI indicates that the codec is ready for more DAC playback data. The signal will remain asserted until the internal playback FIFO is full. PDAK 13 8 I Playback Data Acknowledge. The assertion of this active LO signal indicates that the WR cycle occurring is a DMA write to the playback buffer. ADR1:0 9 & 10 100 & 1 I Codec Addresses. These address pins are asserted by the codec interface logic during a control register/PIO access. The state of these address lines determine which direct register is accessed. RD 60 75 I Read Command Strobe. This active LO signal defines a read cycle from the codec. The cycle may be a read from the control/PIO registers, or the cycles could be a read from the codec’s DMA sample registers. WR 61 76 I Write Command Strobe. This active LO signal indicates a write cycle to the codec. The cycle may be a write to the control/PIO registers, or the cycle could be a write to the codec’s DMA sample registers. CS 59 74 I AD1845 Chip Select. The codec will not respond to any control/PIO cycle accesses unless this active LO signal is LO. This signal is ignored during DMA transfers. DATA7:0 3–6 & 84–87 & I/O Data Bus. These pins transfer data and control information between the codec and 65–68 90–93 the host. DBEN 63 78 O Data Bus Enable. This pin enables the external bus drivers. This signal is normally HI. For control register/PIO cycles, DBEN = (WR or RD) and CS For DMA cycles, DBEN = (WR or RD) and (PDAK or CDAK). DBDIR 62 77 O Data Bus Direction. This pin controls the direction of the data bus transceiver. HI enables writes from the host bus to the AD1845; LO enables reads from the AD1845 to the host bus. This signal is normally HI. For control register/PIO cycles, DBDIR = RD and CS For DMA cycles, DBDIR = RD and (PDAK or CDAK). |
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