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ISP1161A1BMUM Datasheet(PDF) 51 Page - List of Unclassifed Manufacturers |
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ISP1161A1BMUM Datasheet(HTML) 51 Page - List of Unclassifed Manufacturers |
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51 / 137 page  Philips Semiconductors ISP1161A1 USB single-chip host and device controller Product data Rev. 03 — 23 December 2004 50 of 136 9397 750 13961 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Writing a logic 1 to a bit in this register sets the corresponding bit, whereas writing a logic 0 to a bit in this register leaves the corresponding bit unchanged. On a read, the current value of this register is returned. Code (Hex): 04 — read Code (Hex): 84 — write Table 16: HcInterruptEnable register: bit allocation Bit 31 30 29 28 27 26 25 24 Symbol MIE reserved Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 23 22 21 20 19 18 17 16 Symbol reserved Reset 00H Access R/W Bit 15 14 13 12 11 10 9 8 Symbol reserved Reset 00H Access R/W Bit 7 6 5 4 3 2 1 0 Symbol reserved RHSC FNO UE RD SF reserved SO Reset 00000000 Access R/W R/W R/W R/W R/W R/W R/W R/W Table 17: HcInterruptEnable register: bit description Bit Symbol Description 31 MIE MasterInterruptEnable by the HCD: A logic 0 is ignored by the HC. A logic 1 enables interrupt generation by events specified in other bits of this register. 30 to 7 - reserved 6 RHSC 0 — ignore 1 — enable interrupt generation due to Root Hub Status Change 5 FNO 0 — ignore 1 — enable interrupt generation due to Frame Number Overflow 4UE 0 — ignore 1 — enable interrupt generation due to Unrecoverable Error 3RD 0 — ignore 1 — enable interrupt generation due to Resume Detect 2SF 0 — ignore 1 — enable interrupt generation due to Start of Frame 1 - reserved 0SO 0 — ignore 1 — enable interrupt generation due to Scheduling Overrun |
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