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DSPIC33FJ12MC202 Datasheet(PDF) 10 Page - Microchip Technology |
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DSPIC33FJ12MC202 Datasheet(HTML) 10 Page - Microchip Technology |
10 / 284 page dsPIC33FJ12MC201/202 DS70265B-page 8 Preliminary © 2007 Microchip Technology Inc. FIGURE 1-1: dsPIC33FJ12MC201/202 BLOCK DIAGRAM 16 OSC1/CLKI OSC2/CLKO VDD, VSS Timing Generation MCLR Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Precision Reference Band Gap FRC/LPRC Oscillators Regulator Voltage VDDCORE/VCAP IC1,2,7,8 I2C1 PORTA Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features present on each device. Instruction Decode & Control PCH PCL 16 Program Counter 16-bit ALU 23 23 24 23 Instruction Reg PCU 16 x 16 W Register Array ROM Latch 16 EA MUX 16 16 8 Interrupt Controller PSV & Table Data Access Control Block Stack Control Logic Loop Control Logic Data Latch Address Latch Address Latch Program Memory Data Latch Address Bus 16 16 16 16 Data Latch Address Latch 16 X RAM Y RAM 16 Y Data Bus X Data Bus DSP Engine Divide Support 16 Control Signals to Various Blocks ADC1 Timers PORTB Address Generator Units 1-3 CNx UART1 OC/ PWM1-2 QEI PWM 2 Ch PWM 6 Ch Remappable Pins |
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