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AT49F2048 Datasheet(PDF) 2 Page - ATMEL Corporation

Part No. AT49F2048
Description  2-Megabit 128K x 16 5-volt Only CMOS Flash Memory
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Maker  ATMEL [ATMEL Corporation]
Homepage  http://www.atmel.com
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AT49F2048 Datasheet(HTML) 2 Page - ATMEL Corporation

 
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AT49F2048
2
reading from an EPROM; it has standard CE, OE, and WE
inputs to avoid bus connection. The AT49F2048 is a 5-volt-
only, 2 megabit Flash Memory organized as 128K words
contention. Reprogramming the AT49F2048 is performed
by first erasing a block of data and then programming on a
word-by-word basis.
The device is erased by executing the erase command
sequence; the device internally controls the erase opera-
tion. The memory is divided into three blocks for erase
operations. There are two 8K word parameter block sec-
tions and one sector consisting of the boot block and the
main memory array block. The AT49F2048 is programmed
on a word-by-word basis.
The device has the capability to protect the data in the boot
block; this feature is enabled by a command sequence.
Once the boot block programming lockout feature is
enabled, the data in the boot block cannot be changed
when input levels of 5.5 volts or less are used. The typical
number of program and erase cycles is in excess of 10,000
cycles.
The optional 8K word boot block section includes a repro-
gramming lock out feature to provide data integrity. The
boot sector is designed to contain user secure code, and
when the feature is enabled, the boot sector is protected
from being reprogrammed.
Block Diagram
Device Operation
READ: The AT49F2048 is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus conten-
tion.
COMMAND SEQUENCES: When the device is first pow-
ered on it will be reset to the read or standby mode
depending upon the state of the control line inputs. In order
to perform other device functions, a series of command
sequences are entered into the device. The command
sequences are shown in the Command Definitions table
(I/O8 - I/O15 are don't care inputs for the command codes).
The command sequences are written by applying a low
pulse on the WE or CE input with CE or WE low (respec-
tively) and OE high. The address is latched on the falling
edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address loca-
tions used in the command sequences are not affected by
entering the command sequences.
RESET: A RESET input pin is provided to ease some sys-
tem applications. When RESET is at a logic high level, the
device is in its standard operating mode. A low level on the
RESET input halts the present device operation and puts
the outputs of the device in a high impedance state. When
a high level is reasserted on the RESET pin, the device
returns to the Read or Standby mode, depending upon the
state of the control inputs. By applying a 12V
± 0.5V input
signal to the RESET pin the boot block array can be repro-
grammed even if the boot block program lockout feature
has been enabled (see Boot Block Programming Lockout
Override section).
ERASURE: Before a word can be reprogrammed, it must
be erased. The erased state of the memory bits is a logical
“1”. The entire device can be erased at one time by using a
6-byte software code.


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