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AT49F1024 Datasheet(PDF) 2 Page - ATMEL Corporation

Part No. AT49F1024
Description  1-Megabit 64K x 16 5-volt Only Flash Memory
Download  13 Pages
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Maker  ATMEL [ATMEL Corporation]
Homepage  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT49F1024 Datasheet(HTML) 2 Page - ATMEL Corporation

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AT49F1024/1025
2
To allow for simple in-system reprogrammability, the
AT49F1024/1025 does not require high input voltages for
programming. Five-volt-only commands determine the read
and programming operation of the device. Reading data
out of the device is similar to reading from an EPROM.
Reprogramming the AT49F1024/1025 is performed by
erasing a block of data (entire chip or main memory block)
and then programming on a word by word basis. The typi-
cal word programming time is a fast 10
µs. The end of a
program cycle can be optionally detected by the DATA poll-
ing feature. Once the end of a byte program cycle has been
detected, a new access for a read or program can begin.
The typical number of program and erase cycles is in
excess of 10,000 cycles.
The optional 8K words boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being erased or reprogrammed.
Block Diagram
Device Operation
READ : The AT4 9F1 02 4/ 10 25 is accesse d like a n
EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the
address pins is asserted on the outputs. The outputs are
put in the high impedance state whenever CE or OE is
high. This dual-line control gives designers flexibility in pre-
venting bus contention.
CHIP ERASE: When the boot block programming lockout
feature is not enabled, the boot block and the main memory
block will erase together from the same chip erase com-
mand (See command definitions table). If the boot block
lockout function has been enabled, data in the boot section
will not be erased. However, data in the main memory sec-
tion will be erased. After a chip erase, the device will return
to the read mode.
MAIN MEMORY ERASE: As an alternative to the chip
erase, a main memory block erase can be performed which
will erase all bytes not located in the boot block region to an
FFH. Data located in the boot region will not be changed
during a main memory block erase. The Main Memory
Erase command is a six bus cycle operation. The address
(5555H) is latched on the falling edge of the sixth cycle
while the 30H data input is latched on the rising edge of
WE. The main memory erase starts after the rising edge of
WE of the sixth cycle. Please see Main Memory Erase
cycle waveforms. The Main Memory Erase operation is
internally controlled; it will automatically time to completion.
WORD PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
word-by-word basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified t
BP cycle
time. The DATA polling feature may also be used to indi-
cate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
OE, CE, AND WE
LOGIC
Y DECODER
X DECODER
INPUT/OUTPUT
BUFFERS
DATA LATCH
Y-GATING
OPTIONAL BOOT
BLOCK (8K WORDS)
MAIN MEMORY
(56K WORDS)
OE
WE
CE
ADDRESS
INPUTS
VCC
GND
DATA INPUTS/OUTPUTS
I/O15 - I/O0
16
1FFFH
0000H


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