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LP2996MRX Datasheet(PDF) 7 Page - Texas Instruments |
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LP2996MRX Datasheet(HTML) 7 Page - Texas Instruments |
7 / 26 page VTT VREF VDD RS RT CHIPSET MEMORY LP2996-N www.ti.com SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013 Description The LP2996-N is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2. The output, VTT is capable of sinking and sourcing current while regulating the output voltage equal to VDDQ / 2. The output stage has been designed to maintain excellent load regulation while preventing shoot through. The LP2996-N also incorporates two distinct power rails that separates the analog circuitry from the power output stage. This allows a split rail approach to be utilized to decrease internal power dissipation. It also permits the LP2996-N to provide a termination solution for the next generation of DDR-SDRAM memory (DDRII). For new designs, the LP2997 or LP2998 is recommended for DDR-II applications. The LP2996-N can also be used to provide a termination voltage for other logic schemes such as SSTL-3 or HSTL. Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission across the memory bus. This termination scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered with DDR-SDRAM. The most common form of termination is Class II single parallel termination. This involves one RS series resistor from the chipset to the memory and one RT termination resistor. Typical values for RS and RT are 25 Ohms, although these can be changed to scale the current requirements from the LP2996-N. This implementation can be seen below in Figure 20. Figure 20. SSTL-Termination Scheme PIN DESCRIPTIONS AVIN AND PVIN AVIN and PVIN are the input supply pins for the LP2996-N. AVIN is used to supply all the internal control circuitry. PVIN, however, is used exclusively to provide the rail voltage for the output stage used to create VTT. These pins have the capability to work off separate supplies depending on the application. Higher voltages on PVIN will increase the maximum continuous output current because of output RDSON limitations at voltages close to VTT. The disadvantage of high values of PVIN is that the internal power loss will also increase, thermally limiting the design. For SSTL-2 applications, a good compromise would be to connect the AVIN and PVIN directly together at 2.5V. This eliminates the need for bypassing the two supply pins separately. The only limitation on input voltage selection is that PVIN must be equal to or lower than AVIN. It is recommended to connect PVIN to voltage rails equal to or less than 3.3V to prevent the thermal limit from tripping because of excessive internal power dissipation. If the junction temperature exceeds the thermal shutdown than the part will enter a shutdown state identical to the manual shutdown where VTT is tri-stated and VREF remains active. VDDQ VDDQ is the input used to create the internal reference voltage for regulating VTT. The reference voltage is generated from a resistor divider of two internal 50k Ω resistors. This ensures that VTT will track VDDQ / 2 precisely. The optimal implementation of VDDQ is as a remote sense. This can be achieved by connecting VDDQ directly to the 2.5V rail at the DIMM instead of AVIN and PVIN. This ensures that the reference voltage tracks the DDR memory rails precisely without a large voltage drop from the power lines. For SSTL-2 applications VDDQ will be a 2.5V signal, which will create a 1.25V termination voltage at VTT (See Electrical Characteristics Table for exact values of VTT over temperature). Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: LP2996-N |
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