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AT29LV040A Datasheet(PDF) 2 Page - ATMEL Corporation

Part No. AT29LV040A
Description  4 Megabit 512K x 8 3-volt Only 256 Byte Sector CMOS Flash Memory
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT29LV040A Datasheet(HTML) 2 Page - ATMEL Corporation

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Device Operation
The AT29LV040A is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-
line control gives designers flexibility in preventing bus
The AT29LV040A has 2048 individual sectors, each 256-
bytes. Using the software data protection feature, byte
loads are used to enter the 256-bytes of a sector to be
programmed. The AT29LV040A can only be programmed
or reprogrammed using the software data protection fea-
ture. The device is programmed on a sector basis. If a byte
of data within the sector is to be changed, data for the en-
tire 256-byte sector must be loaded into the device. The
AT29LV040A automatically does a sector erase prior to
loading the data into the sector. An erase command is not
Software data protection protects the device from inadver-
tent programming. A series of three program commands
to specific addresses with specific data must be presented
to the device before programming may occur. The same
three program commands must begin each program op-
eration. All software program commands must obey the
sector program timing specifications. Power transitions
will not reset the software data protection feature, however
the software feature will guard against inadvertent pro-
gram cycles during power transitions.
Any attempt to write to the device without the 3-byte com-
mand sequence will start the internal write timers. No data
will be written to the device; however, for the duration of
tWC, a read operation will effectively be a polling operation.
After the software data protection’s 3-byte command code
is given, a byte load is performed by applying a low pulse
on the WE or CE input with CE or WE low (respectively)
and OE high. The address is latched on the falling edge of
Block Diagram
CE or WE, whichever occurs last. The data is latched by
the first rising edge of CE or WE.
The 256-bytes of data must be loaded into each sector.
Any byte that is not loaded during the programming of its
sector will be erased to read FFH. Once the bytes of a
sector are loaded into the device, they are simultaneously
programmed during the internal programming period. Af-
ter the first data byte has been loaded into the device, suc-
cessive bytes are entered in the same manner. Each new
byte to be programmed must have its high to low transition
on WE (or CE) within 150
µs of the low to high transition of
WE (or CE) of the preceding byte. If a high to low transition
is not detected within 150
µs of the last low to high transi-
tion, the load period will end and the internal programming
period will start. A8 to A18 specify the sector address. The
sector address must be valid during each high to low tran-
sition of WE (or CE). A0 to A7 specify the byte address
within the sector. The bytes may be loaded in any order;
sequential loading is not required. Once a programming
operation has been initiated, and for the duration of tWC, a
read operation will effectively be a polling operation.
Hardware features
protect against inadvertent programs to the AT29LV040A
in the following ways: (a) VCC sense— if VCC is below 1.8V
(typical), the program function is inhibited. (b) VCC power
on delay— once VCC has reached the VCC sense level,
the device will automatically time out 10 ms (typical) be-
fore programming. (c) Program inhibit— holding any one
of OE low, CE high or WE high inhibits program cycles. (d)
Noise filter— pulses of less than 15 ns (typical) on the WE
or CE inputs will not initiate a program cycle.
INPUT LEVELS: While operating with a 3.3V
power supply, the address inputs and control inputs (OE,
CE and WE) may be driven from 0 to 5.5V without ad-
versely affecting the operation of the device. The I/O lines
can only be driven from 0 to 3.6V.

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