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AT29LV040A Datasheet(PDF) 1 Page - ATMEL Corporation

Part No. AT29LV040A
Description  4 Megabit 512K x 8 3-volt Only 256 Byte Sector CMOS Flash Memory
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT29LV040A Datasheet(HTML) 1 Page - ATMEL Corporation

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4 Megabit
(512K x 8)
3-volt Only
256 Byte Sector
CMOS Flash
Single Voltage, Range 3V to 3.6V Supply
3-Volt-Only Read and Write Operation
Software Protected Programming
Fast Read Access Time - 200 ns
Low Power Dissipation
15 mA Active Current
µA CMOS Standby Current
Sector Program Operation
Single Cycle Reprogram (Erase and Program)
2048 Sectors (256 bytes/sector)
Internal Address and Data Latches for 256-Bytes
Two 16 KB Boot Blocks with Lockout
Fast Sector Program Cycle Time - 20 ms Max.
Internal Program Control and Timer
DATA Polling for End of Program Detection
Typical Endurance > 10,000 Cycles
CMOS and TTL Compatible Inputs and Outputs
Commercial and Industrial Temperature Ranges
The AT29LV040A is a 3-volt-only in-system Flash Programmable and Erasable Read
Only Memory (PEROM). Its 4 megabits of memory is organized as 524,288 words by
8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS EEPROM technology,
the device offers access times up to 200 ns, and a low 54 mW power dissipation.
When the device is deselected, the CMOS standby current is less than 20
µA. The
device endurance is such that any sector can typically be written to in excess of
10,000 times. The programming algorithm is compatible with other devices in Atmel’s
3-volt-only Flash memories.
To allow for simple in-system reprogrammability, the AT29LV040A does not require
high input voltages for programming. Three-volt-only commands determine the opera-
tion of the device. Reading data out of the device is similar to reading from an EPROM.
Reprogramming the AT29LV040A is performed on a sector basis; 256-bytes of data
are loaded into the device and then simultaneously programmed.
During a reprogram cycle, the address locations and 256-bytes of data are captured
at microprocessor speed and internally latched, freeing the address and data bus for
other operations. Following the initiation of a program cycle, the device will automat-
ically erase the sector and then program the latched data using an internal control
timer. The end of a program cycle can be detected by DATA polling of I/O7. Once the
end of a program cycle has been detected, a new access for a read or program can
Pin Configurations
Pin Name
A0 - A18
Chip Enable
Output Enable
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
No Connect
TSOP Top View
Type 1

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