AT29C257 datasheet(2/12 Pages) ATMEL | 256K 32K x 8 5-volt Only CMOS Flash Memory

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Block Diagram

Device Operation

READ:

The AT29C257 is accessed like a static RAM.

When CE and OE are low and WE is high, the data stored

at the memory location determined by the address pins is

asserted on the outputs. The outputs are put in the high

impedance state whenever CE or OE is high. This dual-

line control gives designers flexibility in preventing bus

contention.

BYTE LOAD:

A byte load is performed by applying a

low pulse on the WE or CE input with CE or WE low (re-

spectively) and OE high. The address is latched on the

falling edge of CE or WE, whichever occurs last. The data

is latched by the first rising edge of CE or WE. Byte loads

are used to enter the 64-bytes of a page to be pro-

grammed or the software codes for data protection and

chip erasure.

PROGRAM:

The device is reprogrammed on a page

basis. If a byte of data within a page is to be changed, data

for the entire page must be loaded into the device. Any

byte that is not loaded during the programming of its page

will be indeterminate. Once the bytes of a page are loaded

into the device, they are simultaneously programmed dur-

ing the internal programming period. After the first data

byte has been loaded into the device, successive bytes

are entered in the same manner. Each new byte to be pro-

grammed must have its high to low transition on WE (or

CE) within 150

µs of the low to high transition of WE (or

CE) of the preceding byte. If a high to low transition is not

detected within 150

µs of the last low to high transition, the

load period will end and the internal programming period

will start. A6 to A14 specify the page address. The page

address must be valid during each high to low transition of

WE (or CE). A0 to A5 specify the byte address within the

page. The bytes may be loaded in any order; sequential

loading is not required. Once a programming operation

has been initiated, and for the duration of tWC, a read op-

eration will effectively be a polling operation.

(continued)

SOFTWARE DATA PROTECTION:

A software control-

led data protection feature is available on the AT29C257.

Once the software protection is enabled a software algo-

rithm must be issued to the device before a program may

be performed. The software protection feature may be en-

abled or disabled by the user; when shipped from Atmel,

the software data protection feature is disabled. To enable

the software data protection, a series of three program

commands to specific addresses with specific data must

be performed. After the software data protection is en-

abled the same three program commands must begin

each program cycle in order for the programs to occur. All

software program commands must obey the page pro-

gram timing specifications. Once set, the software data

protection feature remains active unless its disable com-

mand is issued. Power transitions will not reset the soft-

ware data protection feature, however the software fea-

ture will guard against inadvertent program cycles during

power transitions.

Once set, software data protection will remain active un-

less the disable command sequence is issued.

After setting SDP, any attempt to write to the device with-

out the 3-byte command sequence will start the internal

write timers. No data will be written to the device; however,

for the duration of tWC, a read operation will effectively be

a polling operation.

After the software data protection’s 3-byte command code

is given, a byte load is performed by applying a low pulse

on the WE or CE input with CE or WE low (respectively)

and OE high. The address is latched on the falling edge of

CE or WE, whichever occurs last. The data is latched by

the first rising edge of CE or WE. The 64-bytes of data

must be loaded into each sector by the same procedure as

outlined in the program section under device operation.

4-106

AT29C257

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