Functional Description (Continued)

Table 4. WPEN Operation

WPEN WP

WEN

Protected

Blocks

Unprotected

Blocks

Status

Register

0

X

0

Protected

Protected

Protected

0

X

1

Protected

Writable

Writable

1

Low

0

Protected

Protected

Protected

1

Low

1

Protected

Writable

Protected

X

High

0

Protected

Protected

Protected

X

High

1

Protected

Writable

Writable

READ SEQUENCE (READ):

Reading the AT25128 via

the SO (Serial Output) pin requires the following se-

quence. After the CS line is pulled low to select a device,

the READ op-code is transmitted via the SI line followed

by the byte address to be read (A15-A0, Refer to Table 5).

Upon completion, any data on the SI line will be ignored.

The data (D7-D0) at the specified address is then shifted

out onto the SO line. If only one byte is to be read, the CS

line should be driven high after the data comes out. The

READ sequence can be continued since the byte address

is automatically incremented and data will continue to be

shifted out. When the highest address is reached, the ad-

dress counter will roll over to the lowest address allowing

the entire memory to be read in one continuous READ cy-

cle.

WRITE SEQUENCE (WRITE):

In order to program the

AT25128, two separate instructions must be executed.

First, the device must be write enabled via the Write En-

able (WREN) Instruction. Then a Write (WRITE) Instruc-

tion may be executed. Also, the address of the memory

location(s) to be programmed must be outside the pro-

tected address field location selected by the Block Write

Protection Level. During an internal write cycle, all com-

mands will be ignored except the RDSR instruction.

A Write Instruction requires the following sequence. After

the CS line is pulled low to select the device, the WRITE

op-code is transmitted via the SI line followed by the byte

address (A15-A0) and the data (D7-D0) to be pro-

grammed (Refer to Table 5). Programming will start after

the CS pin is brought high. (The LOW to High transition of

the CS pin must occur during the SCK low time immedi-

ately after clocking in the D0 (LSB) data bit.

The READY/BUSY status of the device can be deter-

mined by initiating a READ STATUS REGISTER (RDSR)

Instruction. If Bit 0 = 1, the WRITE cycle is still in progress.

If Bit 0 = 0, the WRITE cycle has ended. Only the READ

STATUS REGISTER instruction is enabled during the

WRITE programming cycle.

The AT25128 is capable of a 32-byte PAGE WRITE op-

eration. After each byte of data is received, the five low

order address bits are internally incremented by one; the

high order bits of the address will remain constant. If more

than 32-bytes of data are transmitted, the address counter

will roll over and the previously written data will be over-

written. The AT25128 is automatically returned to the write

disable state at the completion of a WRITE cycle.

NOTE: If the device is not Write enabled (WREN), the de-

vice will ignore the Write instruction and will return to the

standby state, when CS is brought high. A new CS falling

edge is required to re-initiate the serial communication.

Table 5. Address Key

Address

AT25128

Don’t Care Bits

8

AT25128