DS92LV3241, DS92LV3242

SNLS314D – SEPTEMBER 2009 – REVISED APRIL 2013

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DS92LV3242 Deserializer PIN DESCRIPTIONS

Pin #

Pin Name

I/O, Type

Description

LVCMOS PARALLEL INTERFACE PINS

5–7,

RxOUT[31:29],

O, LVCMOS

Deserializer Parallel Interface Data Output Pins.

10–14,

RxOUT[28:24],

19–25,

RxOUT[23:17],

28–32,

RxOUT[16:12],

33–39,

RxOUT[11:5],

42–46

RxOUT[4:0]

4

RxCLKOUT

O, LVCMOS

Deserializer Recovered Clock Output. Parallel data rate clock recovered from the embedded

clock.

3

LOCK

O, LVCMOS

LOCK indicates the status of the receiver PLL LOCK = L; deserializer CDR/PLL is not locked,

RxOUT[31:0] and RCLK are TRI-STATED

LOCK = H; deserializer CDR/PLL is locked

CONTROL AND CONFIGURATION PINS

48

R_FB

I, LVCMOS

Rising/Falling Bar Clock Edge Select

R_FB = H; RxOUT clocked on rising edge

R_FB = L; RxOUT clocked on falling edge

50

REN

I, LVCMOS

Deserializer Enable, DES Output Enable Control Input (ACTIVE HIGH)

REN = L; disabled, RxOUT[31:0] and RxCLKOUT TRI-STATED, PLL still operational

REN = H; Enabled (ACTIVE HIGH)

49

PDB

I, LVCMOS

Power Down Bar, Control Input Signal (ACTIVE LOW)

PDB = L; disabled, RxOUT[31:0], RCLK, and LOCK are TRI-STATED in stand-by mode, PLL

is shutdown

PDB = H; Enabled

47

RSVD

I, LVCMOS

Reserved — MUST BE TIED LOW

LVDS SERIAL INTERFACE PINS

51, 53,

RxIN[0:3]+

I, LVDS

Deserializer LVDS Non-Inverted Inputs(+)

57, 59

52, 54,

RxIN[0:3]-

I, LVDS

Deserializer LVDS Inverted Inputs(-)

58, 60

POWER / GROUND PINS

9, 16,

VDD

VDD

Digital Voltage supply, 3.3V

17, 26,

61

8, 15,

VSS

GND

Digital Ground

18, 27,

62

55

VDDA

VDD

Analog LVDS Voltage supply, POWER, 3.3V

56

VSSA

GND

Analog LVDS GROUND

1, 40,

VDDPLL

VDD

Analog Voltage supply PLL VCO POWER, 3.3V

64

2, 41,

VSSPLL

GND

Analog ground, PLL VCO GROUND

63

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

6

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