DS90C383B

SNLS177G – APRIL 2004 – REVISED APRIL 2013

www.ti.com

DS90C383B Pin Description—FPD Link Transmitter

Pin Name

I/O

No.

Description

TxIN

I

28

TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines—FPLINE, FPFRAME and

DRDY (also referred to as HSYNC, VSYNC, Data Enable).

TxOUT+

O

4

Positive LVDS differentiaI data output.

TxOUT-

O

4

Negative LVDS differential data output.

FPSHIFT IN

I

1

TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.

R_FB

I

1

Programmable strobe select (See Table 1).

TxCLK OUT+

O

1

Positive LVDS differential clock output.

TxCLK OUT-

O

1

Negative LVDS differential clock output.

PWR DOWN

I

1

TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down.

See Applications Information.

I

3

Power supply pins for TTL inputs.

GND

I

5

Ground pins for TTL inputs.

I

1

Power supply pin for PLL.

PLL GND

I

2

Ground pins for PLL.

I

1

Power supply pin for LVDS outputs.

LVDS GND

I

3

Ground pins for LVDS outputs.

APPLICATIONS INFORMATION

The DS90C383B are backward compatible with the DS90C383/DS90CF383, DS90C383A/DS90CF383A and are

a pin-for-pin replacement.

This device may also be used as a replacement for the DS90CF583 (5V, 65MHz) and DS90CF581 (5V, 40MHz)

FPD-Link Transmitters with certain considerations/modifications:

2. The DS90C383B transmitter input and control inputs accept 3.3V LVTTL/LVCMOS levels. They are not 5V

tolerant.

3. To implement a falling edge device for the DS90C383B, the R_FB pin (pin 17) may be tied to ground OR left

unconnected (an internal pull-down resistor biases this pin low). Biasing this pin to Vcc implements a rising

edge device.

TRANSMITTER INPUT PINS

The TxIN and control input pins are compatible with LVCMOS and LVTTL levels. These pins are not 5V tolerant.

TRANSMITTER INPUT CLOCK/DATA SEQUENCING

The DS90C383B does not require any special requirement for sequencing of the input clock/data and PD

(PowerDown) signal. The DS90C383B offers a more robust input sequencing feature where the input clock/data

can be inserted after the release of the PD signal. In the case where the clock/data is stopped and reapplied,

such as changing video mode within Graphics Controller, it is not necessary to cycle the PD signal. However,

there are in certain cases where the PD may need to be asserted during these mode changes. In cases where

the source (Graphics Source) may be supplying an unstable clock or spurious noisy clock output to the LVDS

transmitter, the LVDS Transmitter may attempt to lock onto this unstable clock signal but is unable to do so due

the instability or quality of the clock source. The PD signal in these cases should then be asserted once a stable

clock is applied to the LVDS transmitter. Asserting the PWR DOWN pin will effectively place the device in reset

and disable the PLL, enabling the LVDS Transmitter into a power saving standby mode. However, it is still

generally a good practice to assert the PWR DOWN pin or reset the LVDS transmitter whenever the clock/data is

stopped and reapplied but it is not mandatory for the DS90C383B.

SPREAD SPECTRUM CLOCK SUPPORT

The DS90C383B can support Spread Spectrum Clocking signal type inputs. The DS90C383B outputs will

accurately track Spread Spectrum Clock/Data inputs with modulation frequencies of up to 100kHz (max.)with

either center spread of ±2.5% or down spread -5% deviations.

8

Submit Documentation Feedback

Copyright © 2004–2013, Texas Instruments Incorporated

Product Folder Links: DS90C383B