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DRV8803PWPR Datasheet(PDF) 6 Page - Texas Instruments |
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DRV8803PWPR Datasheet(HTML) 6 Page - Texas Instruments |
6 / 19 page nENBL INx OUTx 2 1 3 DRV8803 SLVSAW5B – JULY 2011 – REVISED FEBRUARY 2012 www.ti.com TIMING REQUIREMENTS over operating free-air temperature range (unless otherwise noted) (1) NO. PARAMETER DESCRIPTION MIN MAX UNIT 1 tOE(ENABLE) Enable time, nENBL to output low 50 ns 2 tPD(L-H) Propogation delay time, INx to OUTx, low to high 200 ns 3 tPD(H-L) Propogation delay time, INx to OUTx, high to low 200 ns - tRESET RESET pulse width 20 µs (1) Not production tested. Figure 1. DRV8803 Timing Requirements 6 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): DRV8803 |
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