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NSD-1202

Data Sheet - D e t a i l e d D e s c r i p t i o n

7.8 Duty Cycle Register

A register is used to define the duty cycle (or pulse width) of the driver output signal for each motor. The register value is directly transferred to

the analog part.

Since changing the duty cycle will change the speed of the motor, this register can be used to control the speed of two motors independently.

(Motor speed can also be controlled by varying the voltage; however, one setting applies to both motors. See the previous section, Output

Voltage Register.)

To provide motor independent speed control, the duty cycle may be adjusted from 50% (max speed) down to ~12% (minimum speed). A lower

duty cycle could be used, but may not provide enough vibration amplitude to overcome the load.

The default value for this register set during power up or power down (XPD = LOW) is equal to 00h. In this case the default duty cycle of 50% is

generated. The resulting duty cycle and resolution of single steps is depending on the master clock frequency and the switching frequency of the

driver output.

In the following table an example for 20MHz clock input and 150kHz driver frequency is given. The value of the duty cycle register should not

exceed 50% of the period counter value.

Duty Cycle Register

Min

Typ

Max

Unit

0000 0000

49.6/50.4

%

0000 0001

0.8

%

0000 1101

9.8

%

0001 1011

20.3

%

0010 1000

30.1

%

0011 0101

39.8

%

0100 0010

49.6

%

0100 0011

50.4

%