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Revision 0.2

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NSD-1202

Data Sheet - D e t a i l e d D e s c r i p t i o n

7 Detailed Description

Figure 1 shows the main building blocks of the system:

Voltage reference

Step up converter

I²C interface

Registers

Selectable feedback

Four (4) half bridge drivers

Supplementary blocks such as biasing or power-on reset are not shown. The step-up converter is built as a hysteretic step-up converter. The half

bridge drivers operate rail to rail (VSSP to VDDH). User supplied external components C1, C2, L1 and D1 provide voltage boost and regulation.

The output voltage can be programmed via the I²C interface in 0.5V steps between 24V and 40V. This voltage, along with the duty cycle (or pulse

width) of the drive signal, determines the speed of the motor.

Registers define the switching frequency of the motor, which can be dynamically adjusted from 140 KHz to 180 KHz for optimum motor

performance. Other registers control motor direction and the number of pulses the motor is active (correlating to distance traveled). The XPD

input enables a stand-by mode.

7.1 Step Up Converter

The internal switching converter, together with L1 and C2, form a step up DC/DC converter used to create the high level voltage VDDH in the

range 24 to 40V. The switch includes an over-current detect circuit to ensure safe operation at all times. The output voltage can be programmed

via I²C interface in steps of 0.5V from 24V to 40V. At power up the default output voltage is set to 35V.

7.2 I²C

The I²C interface is used to control the NSD-1202 and set the value of several registers. These registers will define the output voltage (by

changing the resistive feedback divider) as well as the direction and duration of the output driver signals. The period count. duty cycle (or pulse

width) and pulse count registers can be set separately for each motor.

Start/Stop Condition: A HIGH to LOW transition on the SDA line while SCL is HIGH is the start condition for the bus. A LOW to HIGH transition

on the SDA line while SCL is HIGH is the stop condition.

Every byte put on the SDA line must be 8-bits long. Each byte must be followed by an acknowledge bit. Data is transferred with the most

significant bit (MSB) first.

Data transfer with acknowledge is obligatory. The acknowledge-related clock pulse is generated by the master. The receiver must pull down the

SDA line during the acknowledge clock pulse. The NSD-1202 is a slave device on the bus. There are two different access modes:

-Byte write

- Page write

The device can be addressed using 7-bit addressing. The first 6 bits are fixed. The last bit can be set via package pin. Provision will be made for

data collision due to non-synchronization between the external clock and the internally generated clock.