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AS3606 Datasheet(PDF) 58 Page - ams AG |
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AS3606 Datasheet(HTML) 58 Page - ams AG |
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www.austriamicrosystems.com Revision 1.03 57 - 70 AS3606 AS3607 2v2 Data Sheet - R e g i s t e r D e f i n i t i o n Table 49. Second Interrupt Register Name Base Default IRQENRD_1 2-wire serial 00h Offset: 24h Second Interrupt Register Please be aware that writing to this register will enable/disable the corresponding interrupts, while reading gets the actual interrupt status and will clear the register at the same time. It is not possible to read back the interrupt enable/disable settings. This register is reset at a VDD27-POR or XRES input. Bit Bit Name Default Access Bit Description 7 PWRUP_IRQ 0 W Enables interrupt which is invoked whenever a high signal at the PWRUP input pin occurs 0: disable 1: enable x R This bit is set whenever a high level of min. VSUP/3 at the PWRUP input pin occurs (PWRUP pin is commonly connected to the power-up button) 6 GPIO1_IRQ 0 W Enables interrupt which is invoked whenever a high signal at the GPIO1 input pin occurs 0: disable 1: enable x R This bit is set whenever a high level of min. tbd at the GPIO1 input pin occurs 5 GPIO2_IRQ 0 W Enables interrupt which is invoked whenever a high signal at the GPIO2 input pin occurs 0: disable 1: enable x R This bit is set whenever a high level of min. tbd at the GPIO2 input pin occurs 4 GPIO3_IRQ 0 W Enables interrupt which is invoked whenever a high signal at the GPIO3 input pin occurs 0: disable 1: enable x R This bit is set whenever a high level of min. tbd at the GPIO3 input pin occurs 3 GPIO4_IRQ 0 W Enables interrupt which is invoked whenever a high signal at the GPIO4 input pin occurs 0: disable 1: enable x R This bit is set whenever a high level of min. tbd at the GPIO4 input pin occurs 2:0 - 000 n/a |
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