Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

AS3606 Datasheet(PDF) 52 Page - ams AG

Part No. AS3606
Description  System PMU with HV Back Light Driver
Download  71 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  AMSCO [ams AG]
Homepage  http://www.ams.com
Logo 

AS3606 Datasheet(HTML) 52 Page - ams AG

Zoom Inzoom in Zoom Outzoom out
 52 / 71 page
background image
www.austriamicrosystems.com
Revision 1.03
51 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
3:2
GPIO_DIMM_HBN_SEL
<1:0>
00
R/W
Selects input for external dimming or hibernation control
00: disable dimming or hibernation via GPIO
01: GPIO1
10: GPIO2
11: GPIO3
1:0
-
00
n/a
Table 40. BOOST_Cntr1 Register
Name
Base
Default
BOOST_Cntr1
2-wire serial
00h
Offset: 1Bh-1
DCDC step-up Control Register 1
This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Access
Bit Description
7
SU_ON
0
R/W
Enables the DCDC step-up regulator
0: SU switched off
1: SU switched on (will be reset if VFB exceeds the maximum and the
current drops to zero)
6-
0
n/a
5
SU_SLOWDIM
0
R/W
Selects the DCDC step-up regulator external dimming mode
0: for dimming frequencies <1kHz
1: for dimming frequencies >1kHz
4:3
SU_EXTDIM<1:0>
00
R/W
Selects the DCDC step-up external PWM dimming input
00: no ext. dimming
01: CURR1 controlled
10: CURR2 controlled
11: GPIO1/2/3 controlled (selected via GPIO_DIMM_HBN_SEL <1:0>)
2
SU_OVP_OFF
0
R/W
Disables the DCDC step-up over-voltage protection
0: SU OVP switched on
1: SU OVP switched off
1
SU_CURR_FB
0
R/W
Selects the DCDC step-up feedback mode
0: voltage FB via pin FBSU
1: current feedback via CURR1 or CURR2 (automatic select)
0
SU_FASTSKIP
0
R/W
Defines the DCDC step-up regulator output voltage at low loads, when pulse
skipping is active
0: Accurate output voltage, more ripple
1: Elevated output voltage, less ripple
Table 39. Clk_Cntr Register
Name
Base
Default
Clk_Cntr
2-wire serial
00h
Offset: 1Ah-2
Clock Control Register
This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Access
Bit Description


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn