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AS3606 Datasheet(PDF) 42 Page - ams AG

Part No. AS3606
Description  System PMU with HV Back Light Driver
Download  71 Pages
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Maker  AMSCO [ams AG]
Homepage  http://www.ams.com
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AS3606 Datasheet(HTML) 42 Page - ams AG

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www.austriamicrosystems.com
Revision 1.03
41 - 70
AS3606 AS3607 2v2
Data Sheet - R e g i s t e r D e f i n i t i o n
Table 24. GPIO_Cntr Register
Name
Base
Default
GPIO_Cntr
2-wire serial
00h
Offset: 17h-7
GPIO Control Register
This is an extended register and needs to be enabled by writing 111b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Access
Bit Description
7:6
MUX_GPIO43<1:0>
00
R/W
Configures GPIO4 and GPIO3
00: HiZ / HiZ (GPIOs are inputs)
01: xVSUP_low / xCharging
10: xPWRUP / PWRGOOD
11: xEOC / xCharger_active
5
DRIVE_GPIO2
0
R/W
Configures GPIO2 as input or output
0: open drain (output)
1: HiZ (input)
4:3
MUX_GPIO2<1:0>
00
R/W
Configures GPIO2 output mode
00: LOW
01: xVSUP_low
10: HIGH
11: xCharging
2
DRIVE_GPIO1
0
R/W
Configures GPIO1 as input or output
0: HiZ (input)
1: open drain (output)
1:0
MUX_GPIO1<1:0>
00
R/W
Configures GPIO1 output mode
00: xCharging
01: xVSUP_low
10: xPWRUP
11: PWRGOOD
Table 25. PVDD1 Register
Name
Base
Default
PVDD1
2-wire serial
00h
Offset: 18h-1
PVDD1 Control Register
This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first.
This register is reset at a VDD27-POR or XRES input.
Bit
Bit Name
Default
Access
Bit Description
7
PVDD1_ON
0
R/W
Enables PVDD1 regulator
0: PVDD1 switched off
1: PVDD1 switched on
6
ILIM_H_PVDD1
0
R/W
Selects the higher current limit for PVDD1
0: default mode, 150mA
1: 250mA mode
5
LP_PVDD1
0
R/W
Selects the low power mode for PVDD1
0: PVDD1 is in normal operation
1: PVDD1 supply current is reduced
4:0
VSEL_PVDD1<4:0>
00000
R/W
Sets the LDO output voltage in register control mode (default voltage of the
regulator is selected by boot ROM
0x00-0x0F: 1.2V+VSEL*50mV
→ (1.2V - 1.95V)
0x10-0x1F: 2.0V + (VSEL-0x10)*100mV
→ (2.0V-3.5V)


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