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AS3606 Datasheet(PDF) 33 Page - ams AG

Part No. AS3606
Description  System PMU with HV Back Light Driver
Download  71 Pages
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Maker  AMSCO [ams AG]
Homepage  http://www.ams.com
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AS3606 Datasheet(HTML) 33 Page - ams AG

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www.austriamicrosystems.com
Revision 1.03
32 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s
Figure 16. Page Write
Byte Write and Page Write formats are used to write data to the slave.
The transmission begins with the START condition, which is generated by the master when the bus is in IDLE state (the bus is free). The device-
write address is followed by the word address. After the word address any number of data bytes can be sent to the slave. The word address is
incremented internally, in order to write subsequent data bytes on subsequent address locations.
For reading data from the slave device, the master has to change the transfer direction. This can be done either with a repeated START condition
followed by the device-read address, or simply with a new transmission START followed by the device-read address, when the bus is in IDLE
state. The device-read address is always followed by the 1st register byte transmitted from the slave. In Read Mode any number of subsequent
register bytes can be read from the slave. The word address is incremented internally.
Figure 17. Random Read
Random Read and Sequential Read are combined formats. The repeated START condition is used to change the direction after the data transfer
from the master.
The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START condition is followed by the
device-write address and the word address.
In order to change the data direction a repeated START condition is issued on the 1st SCL pulse after the acknowledge bit of the word address
transfer. After the reception of the device-read address, the slave becomes the transmitter. In this state the slave transmits register data located
by the previous received word address vector. The master responds to the data byte with a not-acknowledge, and issues a STOP condition on
the bus.
S
DW
A
WA
A
reg_data 1
A
P
write register
WA++
reg_data 2
A
write register
WA++
reg_data n
A
write register
WA++
...
S
DW
A
WA
A
N
A
read register
WA++
data
Sr
DR
P


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