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AS3606 Datasheet(PDF) 27 Page - ams AG

Part No. AS3606
Description  System PMU with HV Back Light Driver
Download  71 Pages
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Maker  AMSCO [ams AG]
Homepage  http://www.ams.com
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AS3606 Datasheet(HTML) 27 Page - ams AG

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www.austriamicrosystems.com
Revision 1.03
26 - 70
AS3606 AS3607 2v2
Data Sheet - D e t a i l e d D e s c r i p t i o n - S Y S T E M F u n c t i o n s
9 Detailed Description - SYSTEM Functions
9.1 SYSTEM
The system block handles the power up, power down and regulator voltage settings of the PMU.
9.1.1 Power Up/Down Conditions
The chip powers up when one of the following conditions is true:
The chip automatically shuts off if one of the following conditions arises:
9.1.2 Start-up Sequence
The start-up sequence is defined in the boot ROM and will be fixed during the production test.
The sequence and voltage of the regulators can be freely chosen for the start-up sequence with the following limitations:
VDD27 will always start-up, after a ~5ms delay the sequencer will start-up the other chosen regulators with either 0, 1 or 4ms delay each.
A maximum of 6 regulators (no matter of DCDC or LDO) or 5 regulators and a changed GPIO configuration can be chosen for the start-up.
On a 7th time-slot PVDD2 can be started-up, but has reduced setting on the output voltage
PWRGOOD will be activated ~3ms after the last regulator.
XRES will be released 10ms to 110ms (set in the boot ROM) after the last regulator started up.
Table 9. Power UP Conditions
#
Source
Description
1
PWRUP PwUp
ON_KEY High Level at PWRUP pin of >= 1/3 VBATSW
2
VBUS PwUp
USB Plug-In …. High level at VBUS pin of >= 4.5V and >2.7V on VSUP5
Table 10. Power DOWN Conditions
#
Source
Description
1
SERIF MAJOR PwDn
Power-Down by SERIF writing 0h to register 20h
2
Emergency PwDn
Power-Down if PWRUP pin is HIGH for 8sec.
This has to be enabled in register 21h, per default a reset cycle is initiated. It can also be changed to 4s.
3
SERIF Watch-Dog PwDn
write 3h to reg. 20h … enable SERIF watch-dog
Power-Down if no SERIF read is seen for 500ms.
4
Junction-Temp PwDn
Power-Down if junction temperature rises up to 140degC.
This threshold can be lowered with bits <4:0> in reg 21h.
This supervisor can be disabled with bit 2 in reg. 20h.
5
VDD27 LOW PwDn
Power-Down if VDD27 LDO5 has 10% under-voltage for more than 680µs.
This supervisor can get disabled with bit 6 in reg. 21h.
6
CVDD1 LOW PwDn
Power-Down if enabled with bit 7 in reg. 23h and
CVDD1 DCDC has 10% under-voltage for more than 680µs.
7
CVDD2 LOW PwDn
Power-Down if enabled with bit 5 in reg. 23h and
CVDD2 DCDC has 10% under-voltage for more than 680µs.
8
CVDD3 LOW PwDn
Power-Down if enabled with bit 3 in reg. 23h and
CVDD3 DCDC has 10% under-voltage for more than 680µs.
9
VSUP LOW PwDn
Power-Down if VSUPx goes below the defined level in Reg22h (bits <3:1>)
This supervisor has to be enabled with bit 4 in reg. 22h.


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