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EP1AGX60D Datasheet(PDF) 19 Page - Altera Corporation |
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EP1AGX60D Datasheet(HTML) 19 Page - Altera Corporation |
19 / 36 page Functional Description Page 19 Enhanced Configuration (EPC) Devices Datasheet January 2012 Altera Corporation The general guideline for effectiveness of compression is the higher the device logic or routing utilization, the lower the compression ratio (where the compression ratio is defined as the original bitstream size divided by the compressed bitstream size). For Stratix designs, based on a suite of designs with varying amounts of logic utilization, the minimum compression ratio was observed to be 1.9 or a ~47% size reduction for these designs. Table 6 lists sample compression ratios from a suite of Stratix designs. These numbers serve as a guideline, not a specification, to help you allocate sufficient configuration memory to store compressed bitstreams. Programmable Configuration Clock The configuration clock (DCLK) speed is user programmable. One of two clock sources can be used to synthesize the configuration clock; a programmable oscillator or an external clock input pin (EXCLK). The configuration clock frequency can be further synthesized using the clock divider circuitry. This clock can be divided by the N counter to generate your DCLK output. The N divider supports all integer dividers between 1 and 16, as well as a 1.5 divider and a 2.5 divider. The duty cycle for all clock divisions other than non-integer divisions is 50% (for the non-integer dividers, the duty cycle will not be 50%). Figure 5 shows a block diagram of the clock divider unit. The DCLK frequency is limited by the maximum DCLK frequency the FPGA supports. f For more information about the maximum DCLK input frequency supported by the FPGA, refer to the configuration chapter in the appropriate device handbook. Table 6. Stratix Compression Ratios (1) Item Minimum Average Logic Utilization 98% 64% Compression Ratio 1.9 2.3 % Size Reduction 47% 57% Note to Table 6: (1) These numbers are preliminary. They are intended to serve as a guideline, not a specification. Figure 5. Clock Divider Unit Configuration Device Clock Divider Unit Divide by N External Clock (Up to 100 MHz) Internal Oscillator 10 MHz 33 MHz 50 MHz 66 MHz DCLK |
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