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EPC16 Datasheet(PDF) 27 Page - Altera Corporation
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EPC16 Datasheet(HTML) 27 Page - Altera Corporation
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Programming and Configuration File Support
Enhanced Configuration (EPC) Devices Datasheet
The ISP circuitry in the EPC device is compliant with the IEEE Std. 1532 specification.
The IEEE Std. 1532 is a standard that allows concurrent ISP between devices from
For more information about the EPC device JTAG support, refer to the Configuration
Devices BSDL Files page.
EPC devices can also be programmed by third-party flash programmers or on-board
processors using the external flash interface. Programming files (.pof) can be
converted to a Hexadecimal (Intel-Format) File (.hexout) using the Quartus II Convert
utility, for use with the programmers or processors.
Table 11. JTAG Instructions for EPC Devices (1)
00 0101 0101
Allows a snapshot of the state of the EPC device pins to be captured and
examined during normal device operation and permits an initial data pattern
output at the device pins.
00 0000 0000
Allows the external circuitry and board-level interconnections to be tested by
forcing a test pattern at the output pins and capturing results at the input pins.
11 1111 1111
Places the 1-bit bypass register between the TDI and TDO pins, which allow the
BST data to pass synchronously through a selected device to adjacent devices
during normal device operation.
00 0101 1001
Selects the device IDCODE register and places it between TDI and TDO, allowing
the device IDCODE to be serially shifted out to TDO. The device IDCODE for all
EPC devices is the same and shown below:
00 0111 1001
Selects the USERCODE register and places it between TDI and TDO, allowing the
to be serially shifted out the TDO. The 32-bit USERCODE is a
programmable user-defined pattern.
00 0110 0001
This function initiates the FPGA reconfiguration process by pulsing the
pin low, which is connected to the FPGA nCONFIG pin. After this
instruction is updated, the nINIT_CONF pin is pulsed low when the JTAG state
machine enters Run-Test/Idle state. The nINIT_CONF pin is then released
and nCONFIG is pulled high by the resistor after the JTAG state machine goes out
of Run-Test/Idle state. The FPGA configuration starts after nCONFIG goes
high. As a result, the FPGA is configured with the new configuration data stored
in flash using ISP. This function can be added to your programming file (.pof,
.jam, and .jbc) in the Quartus II software by enabling the Initiate configuration
after programming option in the Programmer options window (Options menu).
00 0110 0101
This optional function can be used to hold the nINIT_CONF pin low during
JTAG-based ISP of the EPC device. This feature is useful when the external flash
interface is controlled by an external FPGA or processor. This function prevents
contention on the flash pins when both the controller and external device try to
access the flash simultaneously. Before the EPC device’s controller can access
the flash memory, the external FPGA/processor needs to tri-state its interface to
flash.This can be ensured by resetting the FPGA using the nINIT_CONF, which
drives the nCONFIG pin and keeps the external FPGA or processor in the “reset”
state. The nINIT_CONF pin is released when the initiate configuration
(INIT_CONF) JTAG instruction is issued.
Note to Table 11:
(1) Instruction register length for the EPC device is 10 and boundary scan length is 174.
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