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EPC16 Datasheet(PDF) 29 Page - Altera Corporation

Part No. EPC16
Description  Enhanced Configuration (EPC) Devices Datasheet
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EPC16 Datasheet(HTML) 29 Page - Altera Corporation

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Timing Information
Page 29
Enhanced Configuration (EPC) Devices Datasheet
January 2012
Altera Corporation
Timing Information
Figure 7 shows the configuration timing waveform when you are using an EPC
device.
Table 14 lists the timing parameters when you are using the EPC devices.
tJPXZ
JTAG port valid output to high impedance
25
ns
tJSSU
Capture register setup time
20
ns
tJSH
Capture register hold time
45
ns
tJSCO
Update register clock to output
25
ns
tJSZX
Update register high-impedance to valid output
25
ns
tJSXZ
Update register valid output to high impedance
25
ns
Table 13. JTAG Timing Parameters and Values (Part 2 of 2)
Symbol
Parameter
Min
Max
Unit
Figure 7. Configuration Timing Waveform Using an EPC Device
Notes to Figure 7:
(1) The EPC device drives DCLK low after configuration.
(2) The EPC device drives DATA[] high after configuration.
Byte0
Byte1
Byte2 Byte3
Byten
Tri-State
User Mode
(2)
tOEZX
tPOR
tCH
tCL
tDSU
tCO
tDH
Tri-State
OE/nSTATUS
nCS/CONF_DONE
DCLK
DATA[7..0]
User I/O
INIT_DONE
nINIT_CONF or VCC/nCONFIG
Table 14. EPC Device Configuration Parameters (Part 1 of 2)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fDCLK
DCLK
frequency
40% duty cycle
66.7
MHz
tDCLK
DCLK
period
15
ns
tHC
DCLK
duty cycle high time
40% duty cycle
6
ns
tLC
DCLK
duty cycle low time
40% duty cycle
6
ns
tCE
OE
to first DCLK delay
40
ns
tOE
OE
to first DATA available
40
ns
tOH
DCLK
rising edge to DATA change
(1)
——
ns
tCF (2)
OE
assert to DCLK disable delay
277
ns
tDF (2)
OE
assert to DATA disable delay
277
ns
tRE (3)
DCLK
rising edge to OE
—60
ns
tLOE
OE
assert time to assure reset
60
ns
fECLK
EXCLK
input frequency
40% duty cycle
100
MHz


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