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EPC16 Datasheet(PDF) 10 Page - Altera Corporation
ALTERA [Altera Corporation]
EPC16 Datasheet(HTML) 10 Page - Altera Corporation
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Enhanced Configuration (EPC) Devices Datasheet
Fast Passive Parallel Configuration
Stratix series and APEX II devices can be configured using the EPC device in the FPP
configuration mode. In this mode, the EPC device sends a byte of data on the
pins, which connect to the DATA[7..0] input pins of the FPGA, per DCLK
cycle. Stratix series and APEX II FPGAs receive byte-wide configuration data per DCLK
cycle. Figure 2 shows the EPC device in FPP configuration mode. In this figure, the
external flash interface is not used and hence most flash pins are left unconnected
(with the few noted exceptions).
For more information about configuration interface connections including the pull-up
resistor values, supply voltages, and MSEL pin settings, refer to the configuration
chapter in the appropriate device handbook.
Figure 2. FPP Configuration
Notes to Figure 2:
(1) The V
should be connected to the same supply voltage as the EPC device.
(2) The nINIT_CONF pin is available on EPC devices and has an internal pull-up resistor that is always active. This means an external pull-up
resistor is not required on the nINIT_CONF or nCONFIG signal. The nINIT_CONF pin does not need to be connected if its functionality is not
used. If nINIT_CONF is not used, nCONFIG must be pulled to V
either directly or through a resistor.
(3) The EPC devices’ OE and nCS pins have internal programmable pull-up resistors. If internal pull-up resistors are used, external pull-up resistors
should not be used on these pins. The internal pull-up resistors are used by default in the Quartus
II software. To turn off the internal pull-up
resistors, check the Disable nCS and OE pull-ups on configuration device option when generating programming files.
(4) For PORSEL, PGM, and EXCLK pin connections, refer to Table 10 on page 24.
(5) In the 100-pin PQFP package, you must externally connect the following pins: C-A0 to F-A0, C-A1 to F-A1, C-A15 to F-A15, C-A16 to
, and BYTE# to V
. Additionally, you must make the following pin connections in both 100-pin PQFP and 88-pin UFBGA packages: C-RP#
to F-RP#, C-WE# to F-WE#, TM1 to V
, TM0 to GND, and WP# to V
(6) Connect the FPGA MSEL input pins to select the FPP configuration mode. For more information, refer to the configuration chapter in the
appropriate device handbook.
(7) To protect Intel Flash-based EPC devices content, isolate the V
supply from V
. For more information, refer to “Intel Flash-Based EPC Device
Protection” on page 16.
APEX II Device
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