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74VHC153SJ Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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74VHC153SJ Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 9 page tm May 2007 ©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC153 Rev. 1.2 74VHC153 Dual 4-Input Multiplexer Features ■ High Speed: tPD = 5.0ns at TA = 25°C ■ Low power dissipation: ICC = 4µA (Max.) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (Min.) ■ Power down protection is provided on all inputs ■ Pin and function compatible with 74HC153 General Description The VHC153 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC153 is a high-speed Dual 4-Input Multiplexer with common select inputs and indi- vidual enable inputs for each section. It can select two lines of data from four sources. The two buffered outputs present data in the true (non-inverted) form. In addition to multiplexer operation, the VHC153 can act as a func- tion generator and generate any two functions of three variables. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Information Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering number. Connection Diagram Pin Description Order Number Package Number Package Description 74VHC153M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC153SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC153MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pin Names Description I0a–I3a Side A Data Inputs I0b–I3b Side B Data Inputs S0, S1 Common Select Inputs Ea Side A Enable Input Eb Side B Enable Input Za Side A Output Zb Side B Output |
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