TPS75715, TPS75718, TPS75725, TPS75733 WITH POWER GOOD AND

TPS75701 FAST TRANSIENT RESPONSE 3A LOW DROPOUT

VOLTAGE REGULATORS

SLVS306E − NOVEMBER 2000 − REVISED FEBRUARY 2009

4

POST OFFICE BOX 655303

TPS757xx PG timing diagram

NOTE: VIT −Trip voltage is typically 9% lower than the output voltage (91%VO). VIT− to VIT+ is the hysteresis voltage.

t

t

t

Threshold

Voltage

PG

Output

VIT +(see Note A)

VIN1

VOUT

VIT −

(see Note A)

VUVLO

VUVLO

detailed description

The TPS757xx family includes four fixed-output voltage regulators (1.5 V, 1.8 V, 2.5 V, and 3.3 V), and an

adjustable regulator, the TPS75701 (adjustable from 1.22 V to 5 V). The bandgap voltage is typically 1.22 V.

pin functions

enable (EN)

The EN terminal is an input which enables or shuts down the device. If EN is a logic high, the device will be in

shutdown mode. When EN goes to logic low, the device will be enabled.

power-good (PG)

The PG terminal for the fixed voltage option devices is an open drain, active low output that indicates the status

condition) of the regulated voltage. The open drain output of the PG terminal requires a pullup resistor.

feedback (FB)

FB is an input terminal used for the adjustable-output option and must be connected to the output terminal either

directly, in order to generate the minimum output voltage of 1.22 V, or through an external feedback resistor

divider for other output voltages. The FB connection should be as short as possible. It is essential to route it in

not recommended because it may cause the regulator to oscillate.