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AD835AR-REEL Datasheet(PDF) 10 Page - Analog Devices
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AD835AR-REEL Datasheet(HTML) 10 Page - Analog Devices
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Rev. D | Page 10 of 16
THEORY OF OPERATION
The AD835 is a four-quadrant, voltage output analog multiplier,
fabricated on an advanced dielectrically isolated complementary
bipolar process. In its basic mode, it provides the linear product
of its X and Y voltage inputs. In this mode, the −3 dB output
voltage bandwidth is 250 MHz (with small signal rise time of 1 ns).
Full-scale (−1 V to +1 V) rise to fall times are 2.5 ns (with a
of 150 Ω), and the settling time to 0.1% under the
same conditions is typically 20 ns.
As in earlier multipliers from Analog Devices a unique
summing feature is provided at the Z input. As well as providing
independent ground references for the input and the output and
enhanced versatility, this feature allows the AD835 to operate
with voltage gain. Its X-, Y-, and Z-input voltages are all
nominally ±1 V FS, with an overrange of at least 20%. The
inputs are fully differential at high impedance (100 kΩ||2 pF)
and provide a 70 dB CMRR (f ≤ 1 MHz).
The low impedance output is capable of driving loads as small
as 25 Ω. The peak output can be as large as ±2.2 V minimum
= 150 Ω, or ±2.0 V minimum into R
= 50 Ω. The AD835
has much lower noise than the AD534 or AD734, making it
attractive in low level, signal processing applications, for
example, as a wideband gain control element or modulator.
The multiplier is based on a classic form, having a translinear core,
supported by three (X, Y, and Z) linearized voltage-to-current
converters, and the load driving output amplifier. The scaling
voltage (the denominator U in the equations) is provided by a
band gap reference of novel design, optimized for ultralow noise.
Figure 19 shows the functional block diagram.
In general terms, the AD835 provides the function
where the variables W, U, X, Y, and Z are all voltages. Connected as
a simple multiplier, with X = X1 − X2, Y = Y1 − Y2, and Z = 0
and with a scale factor adjustment (see Figure 19) that sets U = 1 V,
the output can be expressed as
W = XY
X = X1 – X2
Y = Y1 – Y2
XY + Z
Figure 19. Functional Block Diagram
Simplified representations of this sort, where all signals are
presumed expressed in V, are used throughout this data sheet to
avoid the needless use of less intuitive subscripted variables
(such as, V
). All variables as being normalized to 1 V.
For example, the input X can either be stated as being in the −1 V
to +1 V range or simply –1 to +1. The latter representation is found
to facilitate the development of new functions using the AD835.
The explicit inclusion of the denominator, U, is also less helpful, as
in the case of the AD835, if it is not an electrical input variable.
The basic value of U in Equation 1 is nominally 1.05 V. Figure 20,
which shows the basic multiplier connections, also shows how
the effective value of U can be adjusted to have any lower
voltage (usually 1 V) through the use of a resistive divider
between W (Pin 5) and Z (Pin 4). Using the general resistor
values shown, Equation 1can be rewritten as
where Z' is distinguished from the signal Z at Pin 4. It follows that
In this way, the effective value of U can be modified to
U’ = (1 − k)U
without altering the scaling of the Z' input, which is expected because
the only ground reference for the output is through the Z' input.
Therefore, to set U' to 1 V, remembering that the basic value of
U is 1.05 V, R1 must have a nominal value of 20 × R2. The values
shown allow U to be adjusted through the nominal range of
0.95 V to 1.05 V. That is, R2 provides a 5% gain adjustment.
In many applications, the exact gain of the multiplier may not
be very important; in which case, this network may be omitted
entirely, or R2 fixed at 100 Ω.
R1 = (1–k) R
R2 = kR
Figure 20. Multiplier Connections
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